/*****************************************************************************
 * Copyright (c) 2021, RadarEye Technology Co.,Ltd.
 *
 * All rights reserved.
 * ****************************************************************************/
 
  /**
 * @file rcc.h
 * @author RadarEye
 * @version v1.0.0
 *
 * @copyright Copyright (c) 2021, RadarEye Technology Co.,Ltd. All rights reserved.
 */
#ifndef __RCC_H__
#define __RCC_H__

#ifdef __cplusplus
extern "C" {
#endif

#include "n32g45x.h"


#define RCC_24M     24000000
#define RCC_32M     32000000
#define RCC_36M     36000000
#define RCC_48M     48000000
#define RCC_56M     56000000
#define RCC_64M     64000000
#define RCC_72M     72000000
#define RCC_96M     96000000
#define RCC_128M    128000000
#define RCC_144M    144000000


enum
{
    SYSCLK_PLLSRC_HSI,
    SYSCLK_PLLSRC_HSE,
};

/**
 * @brief  Selects HSI as System clock source and configure HCLK, PCLK2
 *         and PCLK1 prescalers.
 */
void SetSysClockToHSI(void);
/**
 * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
 *         and PCLK1 prescalers.
 */
void SetSysClockToHSE(void);
/**
 * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
 *         and PCLK1 prescalers.
 * @param  freq : frequecy of sysclk, like 24000000,36000000...
 * @param  src : SYSCLK_PLLSRC_HSI, SYSCLK_PLLSRC_HSE
 * 
 */
void SetSysClockToPLL(uint32_t freq, uint8_t src);


#ifdef __cplusplus
}
#endif

#endif /* __RCC_H__ */