V9_PMU302/build/system_stm32f3xx.lst

ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 1


   1              		.cpu cortex-m4
   2              		.arch armv7e-m
   3              		.fpu fpv4-sp-d16
   4              		.eabi_attribute 27, 1
   5              		.eabi_attribute 28, 1
   6              		.eabi_attribute 20, 1
   7              		.eabi_attribute 21, 1
   8              		.eabi_attribute 23, 3
   9              		.eabi_attribute 24, 1
  10              		.eabi_attribute 25, 1
  11              		.eabi_attribute 26, 1
  12              		.eabi_attribute 30, 6
  13              		.eabi_attribute 34, 1
  14              		.eabi_attribute 18, 4
  15              		.file	"system_stm32f3xx.c"
  16              		.text
  17              	.Ltext0:
  18              		.cfi_sections	.debug_frame
  19              		.global	SystemCoreClock
  20              		.section	.data.SystemCoreClock,"aw"
  21              		.align	2
  24              	SystemCoreClock:
  25 0000 00127A00 		.word	8000000
  26              		.global	AHBPrescTable
  27              		.section	.rodata.AHBPrescTable,"a"
  28              		.align	2
  31              	AHBPrescTable:
  32 0000 00000000 		.ascii	"\000\000\000\000\000\000\000\000\001\002\003\004\006"
  32      00000000 
  32      01020304 
  32      06
  33 000d 070809   		.ascii	"\007\010\011"
  34              		.global	APBPrescTable
  35              		.section	.rodata.APBPrescTable,"a"
  36              		.align	2
  39              	APBPrescTable:
  40 0000 00000000 		.ascii	"\000\000\000\000\001\002\003\004"
  40      01020304 
  41              		.section	.text.SystemInit,"ax",%progbits
  42              		.align	1
  43              		.global	SystemInit
  44              		.syntax unified
  45              		.thumb
  46              		.thumb_func
  48              	SystemInit:
  49              	.LFB130:
  50              		.file 1 "Core/Src/system_stm32f3xx.c"
   1:Core/Src/system_stm32f3xx.c **** /**
   2:Core/Src/system_stm32f3xx.c ****   ******************************************************************************
   3:Core/Src/system_stm32f3xx.c ****   * @file    system_stm32f3xx.c
   4:Core/Src/system_stm32f3xx.c ****   * @author  MCD Application Team
   5:Core/Src/system_stm32f3xx.c ****   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   6:Core/Src/system_stm32f3xx.c ****   *
   7:Core/Src/system_stm32f3xx.c ****   * 1. This file provides two functions and one global variable to be called from
   8:Core/Src/system_stm32f3xx.c ****   *    user application:
   9:Core/Src/system_stm32f3xx.c ****   *      - SystemInit(): This function is called at startup just after reset and 
  10:Core/Src/system_stm32f3xx.c ****   *                      before branch to main program. This call is made inside
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 2


  11:Core/Src/system_stm32f3xx.c ****   *                      the "startup_stm32f3xx.s" file.
  12:Core/Src/system_stm32f3xx.c ****   *
  13:Core/Src/system_stm32f3xx.c ****   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  14:Core/Src/system_stm32f3xx.c ****   *                                  by the user application to setup the SysTick
  15:Core/Src/system_stm32f3xx.c ****   *                                  timer or configure other parameters.
  16:Core/Src/system_stm32f3xx.c ****   *
  17:Core/Src/system_stm32f3xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  18:Core/Src/system_stm32f3xx.c ****   *                                 be called whenever the core clock is changed
  19:Core/Src/system_stm32f3xx.c ****   *                                 during program execution.
  20:Core/Src/system_stm32f3xx.c ****   *
  21:Core/Src/system_stm32f3xx.c ****   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  22:Core/Src/system_stm32f3xx.c ****   *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
  23:Core/Src/system_stm32f3xx.c ****   *    configure the system clock before to branch to main program.
  24:Core/Src/system_stm32f3xx.c ****   *
  25:Core/Src/system_stm32f3xx.c ****   * 3. This file configures the system clock as follows:
  26:Core/Src/system_stm32f3xx.c ****   *=============================================================================
  27:Core/Src/system_stm32f3xx.c ****   *                         Supported STM32F3xx device
  28:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  29:Core/Src/system_stm32f3xx.c ****   *        System Clock source                    | HSI
  30:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  31:Core/Src/system_stm32f3xx.c ****   *        SYSCLK(Hz)                             | 8000000
  32:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  33:Core/Src/system_stm32f3xx.c ****   *        HCLK(Hz)                               | 8000000
  34:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  35:Core/Src/system_stm32f3xx.c ****   *        AHB Prescaler                          | 1
  36:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  37:Core/Src/system_stm32f3xx.c ****   *        APB2 Prescaler                         | 1
  38:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  39:Core/Src/system_stm32f3xx.c ****   *        APB1 Prescaler                         | 1
  40:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  41:Core/Src/system_stm32f3xx.c ****   *        USB Clock                              | DISABLE
  42:Core/Src/system_stm32f3xx.c ****   *-----------------------------------------------------------------------------
  43:Core/Src/system_stm32f3xx.c ****   *=============================================================================
  44:Core/Src/system_stm32f3xx.c ****   ******************************************************************************
  45:Core/Src/system_stm32f3xx.c ****   * @attention
  46:Core/Src/system_stm32f3xx.c ****   *
  47:Core/Src/system_stm32f3xx.c ****   * Copyright (c) 2016 STMicroelectronics.
  48:Core/Src/system_stm32f3xx.c ****   * All rights reserved.
  49:Core/Src/system_stm32f3xx.c ****   *
  50:Core/Src/system_stm32f3xx.c ****   * This software is licensed under terms that can be found in the LICENSE file
  51:Core/Src/system_stm32f3xx.c ****   * in the root directory of this software component.
  52:Core/Src/system_stm32f3xx.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  53:Core/Src/system_stm32f3xx.c ****   *
  54:Core/Src/system_stm32f3xx.c ****   ******************************************************************************
  55:Core/Src/system_stm32f3xx.c ****   */
  56:Core/Src/system_stm32f3xx.c **** 
  57:Core/Src/system_stm32f3xx.c **** /** @addtogroup CMSIS
  58:Core/Src/system_stm32f3xx.c ****   * @{
  59:Core/Src/system_stm32f3xx.c ****   */
  60:Core/Src/system_stm32f3xx.c **** 
  61:Core/Src/system_stm32f3xx.c **** /** @addtogroup stm32f3xx_system
  62:Core/Src/system_stm32f3xx.c ****   * @{
  63:Core/Src/system_stm32f3xx.c ****   */
  64:Core/Src/system_stm32f3xx.c **** 
  65:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Includes
  66:Core/Src/system_stm32f3xx.c ****   * @{
  67:Core/Src/system_stm32f3xx.c ****   */
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 3


  68:Core/Src/system_stm32f3xx.c **** 
  69:Core/Src/system_stm32f3xx.c **** #include "stm32f3xx.h"
  70:Core/Src/system_stm32f3xx.c **** 
  71:Core/Src/system_stm32f3xx.c **** /**
  72:Core/Src/system_stm32f3xx.c ****   * @}
  73:Core/Src/system_stm32f3xx.c ****   */
  74:Core/Src/system_stm32f3xx.c **** 
  75:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
  76:Core/Src/system_stm32f3xx.c ****   * @{
  77:Core/Src/system_stm32f3xx.c ****   */
  78:Core/Src/system_stm32f3xx.c **** 
  79:Core/Src/system_stm32f3xx.c **** /**
  80:Core/Src/system_stm32f3xx.c ****   * @}
  81:Core/Src/system_stm32f3xx.c ****   */
  82:Core/Src/system_stm32f3xx.c **** 
  83:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Defines
  84:Core/Src/system_stm32f3xx.c ****   * @{
  85:Core/Src/system_stm32f3xx.c ****   */
  86:Core/Src/system_stm32f3xx.c **** #if !defined  (HSE_VALUE) 
  87:Core/Src/system_stm32f3xx.c ****   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
  88:Core/Src/system_stm32f3xx.c ****                                                 This value can be provided and adapted by the user 
  89:Core/Src/system_stm32f3xx.c **** #endif /* HSE_VALUE */
  90:Core/Src/system_stm32f3xx.c **** 
  91:Core/Src/system_stm32f3xx.c **** #if !defined  (HSI_VALUE)
  92:Core/Src/system_stm32f3xx.c ****   #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
  93:Core/Src/system_stm32f3xx.c ****                                                 This value can be provided and adapted by the user 
  94:Core/Src/system_stm32f3xx.c **** #endif /* HSI_VALUE */
  95:Core/Src/system_stm32f3xx.c **** 
  96:Core/Src/system_stm32f3xx.c **** /* Note: Following vector table addresses must be defined in line with linker
  97:Core/Src/system_stm32f3xx.c ****          configuration. */
  98:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
  99:Core/Src/system_stm32f3xx.c ****      anywhere in Flash or Sram, else the vector table is kept at the automatic
 100:Core/Src/system_stm32f3xx.c ****      remap of boot address selected */
 101:Core/Src/system_stm32f3xx.c **** /* #define USER_VECT_TAB_ADDRESS */
 102:Core/Src/system_stm32f3xx.c **** 
 103:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
 104:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
 105:Core/Src/system_stm32f3xx.c ****      in Sram else user remap will be done in Flash. */
 106:Core/Src/system_stm32f3xx.c **** /* #define VECT_TAB_SRAM */
 107:Core/Src/system_stm32f3xx.c **** #if defined(VECT_TAB_SRAM)
 108:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
 109:Core/Src/system_stm32f3xx.c ****                                                      This value must be a multiple of 0x200. */
 110:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
 111:Core/Src/system_stm32f3xx.c ****                                                      This value must be a multiple of 0x200. */
 112:Core/Src/system_stm32f3xx.c **** #else
 113:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
 114:Core/Src/system_stm32f3xx.c ****                                                      This value must be a multiple of 0x200. */
 115:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
 116:Core/Src/system_stm32f3xx.c ****                                                      This value must be a multiple of 0x200. */
 117:Core/Src/system_stm32f3xx.c **** #endif /* VECT_TAB_SRAM */
 118:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 119:Core/Src/system_stm32f3xx.c **** 
 120:Core/Src/system_stm32f3xx.c **** /******************************************************************************/
 121:Core/Src/system_stm32f3xx.c **** /**
 122:Core/Src/system_stm32f3xx.c ****   * @}
 123:Core/Src/system_stm32f3xx.c ****   */
 124:Core/Src/system_stm32f3xx.c **** 
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 4


 125:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Macros
 126:Core/Src/system_stm32f3xx.c ****   * @{
 127:Core/Src/system_stm32f3xx.c ****   */
 128:Core/Src/system_stm32f3xx.c **** 
 129:Core/Src/system_stm32f3xx.c **** /**
 130:Core/Src/system_stm32f3xx.c ****   * @}
 131:Core/Src/system_stm32f3xx.c ****   */
 132:Core/Src/system_stm32f3xx.c **** 
 133:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Variables
 134:Core/Src/system_stm32f3xx.c ****   * @{
 135:Core/Src/system_stm32f3xx.c ****   */
 136:Core/Src/system_stm32f3xx.c ****   /* This variable is updated in three ways:
 137:Core/Src/system_stm32f3xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
 138:Core/Src/system_stm32f3xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 139:Core/Src/system_stm32f3xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 140:Core/Src/system_stm32f3xx.c ****          Note: If you use this function to configure the system clock there is no need to
 141:Core/Src/system_stm32f3xx.c ****                call the 2 first functions listed above, since SystemCoreClock variable is 
 142:Core/Src/system_stm32f3xx.c ****                updated automatically.
 143:Core/Src/system_stm32f3xx.c ****   */
 144:Core/Src/system_stm32f3xx.c **** uint32_t SystemCoreClock = 8000000;
 145:Core/Src/system_stm32f3xx.c **** 
 146:Core/Src/system_stm32f3xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 147:Core/Src/system_stm32f3xx.c **** const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 148:Core/Src/system_stm32f3xx.c **** 
 149:Core/Src/system_stm32f3xx.c **** /**
 150:Core/Src/system_stm32f3xx.c ****   * @}
 151:Core/Src/system_stm32f3xx.c ****   */
 152:Core/Src/system_stm32f3xx.c **** 
 153:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
 154:Core/Src/system_stm32f3xx.c ****   * @{
 155:Core/Src/system_stm32f3xx.c ****   */
 156:Core/Src/system_stm32f3xx.c **** 
 157:Core/Src/system_stm32f3xx.c **** /**
 158:Core/Src/system_stm32f3xx.c ****   * @}
 159:Core/Src/system_stm32f3xx.c ****   */
 160:Core/Src/system_stm32f3xx.c **** 
 161:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Functions
 162:Core/Src/system_stm32f3xx.c ****   * @{
 163:Core/Src/system_stm32f3xx.c ****   */
 164:Core/Src/system_stm32f3xx.c **** 
 165:Core/Src/system_stm32f3xx.c **** /**
 166:Core/Src/system_stm32f3xx.c ****   * @brief  Setup the microcontroller system
 167:Core/Src/system_stm32f3xx.c ****   * @param  None
 168:Core/Src/system_stm32f3xx.c ****   * @retval None
 169:Core/Src/system_stm32f3xx.c ****   */
 170:Core/Src/system_stm32f3xx.c **** void SystemInit(void)
 171:Core/Src/system_stm32f3xx.c **** {
  51              		.loc 1 171 1
  52              		.cfi_startproc
  53              		@ args = 0, pretend = 0, frame = 0
  54              		@ frame_needed = 1, uses_anonymous_args = 0
  55              		@ link register save eliminated.
  56 0000 80B4     		push	{r7}
  57              	.LCFI0:
  58              		.cfi_def_cfa_offset 4
  59              		.cfi_offset 7, -4
  60 0002 00AF     		add	r7, sp, #0
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 5


  61              	.LCFI1:
  62              		.cfi_def_cfa_register 7
 172:Core/Src/system_stm32f3xx.c **** /* FPU settings --------------------------------------------------------------*/
 173:Core/Src/system_stm32f3xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 174:Core/Src/system_stm32f3xx.c ****   SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
  63              		.loc 1 174 14
  64 0004 064B     		ldr	r3, .L2
  65 0006 D3F88830 		ldr	r3, [r3, #136]
  66 000a 054A     		ldr	r2, .L2
  67 000c 43F47003 		orr	r3, r3, #15728640
  68 0010 C2F88830 		str	r3, [r2, #136]
 175:Core/Src/system_stm32f3xx.c **** #endif
 176:Core/Src/system_stm32f3xx.c **** 
 177:Core/Src/system_stm32f3xx.c ****   /* Configure the Vector Table location -------------------------------------*/
 178:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
 179:Core/Src/system_stm32f3xx.c ****   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM 
 180:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 181:Core/Src/system_stm32f3xx.c **** }
  69              		.loc 1 181 1
  70 0014 00BF     		nop
  71 0016 BD46     		mov	sp, r7
  72              	.LCFI2:
  73              		.cfi_def_cfa_register 13
  74              		@ sp needed
  75 0018 5DF8047B 		ldr	r7, [sp], #4
  76              	.LCFI3:
  77              		.cfi_restore 7
  78              		.cfi_def_cfa_offset 0
  79 001c 7047     		bx	lr
  80              	.L3:
  81 001e 00BF     		.align	2
  82              	.L2:
  83 0020 00ED00E0 		.word	-536810240
  84              		.cfi_endproc
  85              	.LFE130:
  87              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
  88              		.align	1
  89              		.global	SystemCoreClockUpdate
  90              		.syntax unified
  91              		.thumb
  92              		.thumb_func
  94              	SystemCoreClockUpdate:
  95              	.LFB131:
 182:Core/Src/system_stm32f3xx.c **** 
 183:Core/Src/system_stm32f3xx.c **** /**
 184:Core/Src/system_stm32f3xx.c ****    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 185:Core/Src/system_stm32f3xx.c ****   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 186:Core/Src/system_stm32f3xx.c ****   *         be used by the user application to setup the SysTick timer or configure
 187:Core/Src/system_stm32f3xx.c ****   *         other parameters.
 188:Core/Src/system_stm32f3xx.c ****   *
 189:Core/Src/system_stm32f3xx.c ****   * @note   Each time the core clock (HCLK) changes, this function must be called
 190:Core/Src/system_stm32f3xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
 191:Core/Src/system_stm32f3xx.c ****   *         based on this variable will be incorrect.
 192:Core/Src/system_stm32f3xx.c ****   *
 193:Core/Src/system_stm32f3xx.c ****   * @note   - The system frequency computed by this function is not the real
 194:Core/Src/system_stm32f3xx.c ****   *           frequency in the chip. It is calculated based on the predefined
 195:Core/Src/system_stm32f3xx.c ****   *           constant and the selected clock source:
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 6


 196:Core/Src/system_stm32f3xx.c ****   *
 197:Core/Src/system_stm32f3xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 198:Core/Src/system_stm32f3xx.c ****   *
 199:Core/Src/system_stm32f3xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 200:Core/Src/system_stm32f3xx.c ****   *
 201:Core/Src/system_stm32f3xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 202:Core/Src/system_stm32f3xx.c ****   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 203:Core/Src/system_stm32f3xx.c ****   *
 204:Core/Src/system_stm32f3xx.c ****   *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
 205:Core/Src/system_stm32f3xx.c ****   *             8 MHz) but the real value may vary depending on the variations
 206:Core/Src/system_stm32f3xx.c ****   *             in voltage and temperature.
 207:Core/Src/system_stm32f3xx.c ****   *
 208:Core/Src/system_stm32f3xx.c ****   *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
 209:Core/Src/system_stm32f3xx.c ****   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 210:Core/Src/system_stm32f3xx.c ****   *              frequency of the crystal used. Otherwise, this function may
 211:Core/Src/system_stm32f3xx.c ****   *              have wrong result.
 212:Core/Src/system_stm32f3xx.c ****   *
 213:Core/Src/system_stm32f3xx.c ****   *         - The result of this function could be not correct when using fractional
 214:Core/Src/system_stm32f3xx.c ****   *           value for HSE crystal.
 215:Core/Src/system_stm32f3xx.c ****   *
 216:Core/Src/system_stm32f3xx.c ****   * @param  None
 217:Core/Src/system_stm32f3xx.c ****   * @retval None
 218:Core/Src/system_stm32f3xx.c ****   */
 219:Core/Src/system_stm32f3xx.c **** void SystemCoreClockUpdate (void)
 220:Core/Src/system_stm32f3xx.c **** {
  96              		.loc 1 220 1
  97              		.cfi_startproc
  98              		@ args = 0, pretend = 0, frame = 16
  99              		@ frame_needed = 1, uses_anonymous_args = 0
 100              		@ link register save eliminated.
 101 0000 80B4     		push	{r7}
 102              	.LCFI4:
 103              		.cfi_def_cfa_offset 4
 104              		.cfi_offset 7, -4
 105 0002 85B0     		sub	sp, sp, #20
 106              	.LCFI5:
 107              		.cfi_def_cfa_offset 24
 108 0004 00AF     		add	r7, sp, #0
 109              	.LCFI6:
 110              		.cfi_def_cfa_register 7
 221:Core/Src/system_stm32f3xx.c ****   uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
 111              		.loc 1 221 12
 112 0006 0023     		movs	r3, #0
 113 0008 FB60     		str	r3, [r7, #12]
 114              		.loc 1 221 21
 115 000a 0023     		movs	r3, #0
 116 000c BB60     		str	r3, [r7, #8]
 117              		.loc 1 221 34
 118 000e 0023     		movs	r3, #0
 119 0010 7B60     		str	r3, [r7, #4]
 120              		.loc 1 221 49
 121 0012 0023     		movs	r3, #0
 122 0014 3B60     		str	r3, [r7]
 222:Core/Src/system_stm32f3xx.c **** 
 223:Core/Src/system_stm32f3xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
 224:Core/Src/system_stm32f3xx.c ****   tmp = RCC->CFGR & RCC_CFGR_SWS;
 123              		.loc 1 224 12
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 7


 124 0016 2D4B     		ldr	r3, .L12
 125 0018 5B68     		ldr	r3, [r3, #4]
 126              		.loc 1 224 7
 127 001a 03F00C03 		and	r3, r3, #12
 128 001e FB60     		str	r3, [r7, #12]
 225:Core/Src/system_stm32f3xx.c **** 
 226:Core/Src/system_stm32f3xx.c ****   switch (tmp)
 129              		.loc 1 226 3
 130 0020 FB68     		ldr	r3, [r7, #12]
 131 0022 082B     		cmp	r3, #8
 132 0024 11D0     		beq	.L5
 133 0026 FB68     		ldr	r3, [r7, #12]
 134 0028 082B     		cmp	r3, #8
 135 002a 36D8     		bhi	.L6
 136 002c FB68     		ldr	r3, [r7, #12]
 137 002e 002B     		cmp	r3, #0
 138 0030 03D0     		beq	.L7
 139 0032 FB68     		ldr	r3, [r7, #12]
 140 0034 042B     		cmp	r3, #4
 141 0036 04D0     		beq	.L8
 142 0038 2FE0     		b	.L6
 143              	.L7:
 227:Core/Src/system_stm32f3xx.c ****   {
 228:Core/Src/system_stm32f3xx.c ****     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
 229:Core/Src/system_stm32f3xx.c ****       SystemCoreClock = HSI_VALUE;
 144              		.loc 1 229 23
 145 003a 254B     		ldr	r3, .L12+4
 146 003c 254A     		ldr	r2, .L12+8
 147 003e 1A60     		str	r2, [r3]
 230:Core/Src/system_stm32f3xx.c ****       break;
 148              		.loc 1 230 7
 149 0040 2FE0     		b	.L9
 150              	.L8:
 231:Core/Src/system_stm32f3xx.c ****     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
 232:Core/Src/system_stm32f3xx.c ****       SystemCoreClock = HSE_VALUE;
 151              		.loc 1 232 23
 152 0042 234B     		ldr	r3, .L12+4
 153 0044 234A     		ldr	r2, .L12+8
 154 0046 1A60     		str	r2, [r3]
 233:Core/Src/system_stm32f3xx.c ****       break;
 155              		.loc 1 233 7
 156 0048 2BE0     		b	.L9
 157              	.L5:
 234:Core/Src/system_stm32f3xx.c ****     case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
 235:Core/Src/system_stm32f3xx.c ****       /* Get PLL clock source and multiplication factor ----------------------*/
 236:Core/Src/system_stm32f3xx.c ****       pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
 158              		.loc 1 236 20
 159 004a 204B     		ldr	r3, .L12
 160 004c 5B68     		ldr	r3, [r3, #4]
 161              		.loc 1 236 15
 162 004e 03F47013 		and	r3, r3, #3932160
 163 0052 BB60     		str	r3, [r7, #8]
 237:Core/Src/system_stm32f3xx.c ****       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 164              		.loc 1 237 22
 165 0054 1D4B     		ldr	r3, .L12
 166 0056 5B68     		ldr	r3, [r3, #4]
 167              		.loc 1 237 17
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 8


 168 0058 03F48033 		and	r3, r3, #65536
 169 005c 7B60     		str	r3, [r7, #4]
 238:Core/Src/system_stm32f3xx.c ****       pllmull = ( pllmull >> 18) + 2;
 170              		.loc 1 238 27
 171 005e BB68     		ldr	r3, [r7, #8]
 172 0060 9B0C     		lsrs	r3, r3, #18
 173              		.loc 1 238 15
 174 0062 0233     		adds	r3, r3, #2
 175 0064 BB60     		str	r3, [r7, #8]
 239:Core/Src/system_stm32f3xx.c **** 
 240:Core/Src/system_stm32f3xx.c **** #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
 241:Core/Src/system_stm32f3xx.c ****         predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 242:Core/Src/system_stm32f3xx.c ****       if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
 243:Core/Src/system_stm32f3xx.c ****       {
 244:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 245:Core/Src/system_stm32f3xx.c ****         SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
 246:Core/Src/system_stm32f3xx.c ****       }
 247:Core/Src/system_stm32f3xx.c ****       else
 248:Core/Src/system_stm32f3xx.c ****       {
 249:Core/Src/system_stm32f3xx.c ****         /* HSI oscillator clock selected as PREDIV1 clock entry */
 250:Core/Src/system_stm32f3xx.c ****         SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
 251:Core/Src/system_stm32f3xx.c ****       }
 252:Core/Src/system_stm32f3xx.c **** #else      
 253:Core/Src/system_stm32f3xx.c ****       if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
 176              		.loc 1 253 10
 177 0066 7B68     		ldr	r3, [r7, #4]
 178 0068 002B     		cmp	r3, #0
 179 006a 06D1     		bne	.L10
 254:Core/Src/system_stm32f3xx.c ****       {
 255:Core/Src/system_stm32f3xx.c ****         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 256:Core/Src/system_stm32f3xx.c ****         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 180              		.loc 1 256 44
 181 006c BB68     		ldr	r3, [r7, #8]
 182 006e 1A4A     		ldr	r2, .L12+12
 183 0070 02FB03F3 		mul	r3, r2, r3
 184              		.loc 1 256 25
 185 0074 164A     		ldr	r2, .L12+4
 186 0076 1360     		str	r3, [r2]
 257:Core/Src/system_stm32f3xx.c ****       }
 258:Core/Src/system_stm32f3xx.c ****       else
 259:Core/Src/system_stm32f3xx.c ****       {
 260:Core/Src/system_stm32f3xx.c ****         predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 261:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 262:Core/Src/system_stm32f3xx.c ****         SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
 263:Core/Src/system_stm32f3xx.c ****       }
 264:Core/Src/system_stm32f3xx.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
 265:Core/Src/system_stm32f3xx.c ****       break;
 187              		.loc 1 265 7
 188 0078 13E0     		b	.L9
 189              	.L10:
 260:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 190              		.loc 1 260 28
 191 007a 144B     		ldr	r3, .L12
 192 007c DB6A     		ldr	r3, [r3, #44]
 260:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 193              		.loc 1 260 36
 194 007e 03F00F03 		and	r3, r3, #15
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 9


 260:Core/Src/system_stm32f3xx.c ****         /* HSE oscillator clock selected as PREDIV1 clock entry */
 195              		.loc 1 260 22
 196 0082 0133     		adds	r3, r3, #1
 197 0084 3B60     		str	r3, [r7]
 262:Core/Src/system_stm32f3xx.c ****       }
 198              		.loc 1 262 38
 199 0086 134A     		ldr	r2, .L12+8
 200 0088 3B68     		ldr	r3, [r7]
 201 008a B2FBF3F3 		udiv	r3, r2, r3
 262:Core/Src/system_stm32f3xx.c ****       }
 202              		.loc 1 262 54
 203 008e BA68     		ldr	r2, [r7, #8]
 204 0090 02FB03F3 		mul	r3, r2, r3
 262:Core/Src/system_stm32f3xx.c ****       }
 205              		.loc 1 262 25
 206 0094 0E4A     		ldr	r2, .L12+4
 207 0096 1360     		str	r3, [r2]
 208              		.loc 1 265 7
 209 0098 03E0     		b	.L9
 210              	.L6:
 266:Core/Src/system_stm32f3xx.c ****     default: /* HSI used as system clock */
 267:Core/Src/system_stm32f3xx.c ****       SystemCoreClock = HSI_VALUE;
 211              		.loc 1 267 23
 212 009a 0D4B     		ldr	r3, .L12+4
 213 009c 0D4A     		ldr	r2, .L12+8
 214 009e 1A60     		str	r2, [r3]
 268:Core/Src/system_stm32f3xx.c ****       break;
 215              		.loc 1 268 7
 216 00a0 00BF     		nop
 217              	.L9:
 269:Core/Src/system_stm32f3xx.c ****   }
 270:Core/Src/system_stm32f3xx.c ****   /* Compute HCLK clock frequency ----------------*/
 271:Core/Src/system_stm32f3xx.c ****   /* Get HCLK prescaler */
 272:Core/Src/system_stm32f3xx.c ****   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 218              		.loc 1 272 28
 219 00a2 0A4B     		ldr	r3, .L12
 220 00a4 5B68     		ldr	r3, [r3, #4]
 221              		.loc 1 272 52
 222 00a6 1B09     		lsrs	r3, r3, #4
 223 00a8 03F00F03 		and	r3, r3, #15
 224              		.loc 1 272 22
 225 00ac 0B4A     		ldr	r2, .L12+16
 226 00ae D35C     		ldrb	r3, [r2, r3]	@ zero_extendqisi2
 227              		.loc 1 272 7
 228 00b0 FB60     		str	r3, [r7, #12]
 273:Core/Src/system_stm32f3xx.c ****   /* HCLK clock frequency */
 274:Core/Src/system_stm32f3xx.c ****   SystemCoreClock >>= tmp;
 229              		.loc 1 274 19
 230 00b2 074B     		ldr	r3, .L12+4
 231 00b4 1A68     		ldr	r2, [r3]
 232 00b6 FB68     		ldr	r3, [r7, #12]
 233 00b8 22FA03F3 		lsr	r3, r2, r3
 234 00bc 044A     		ldr	r2, .L12+4
 235 00be 1360     		str	r3, [r2]
 275:Core/Src/system_stm32f3xx.c **** }
 236              		.loc 1 275 1
 237 00c0 00BF     		nop
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 10


 238 00c2 1437     		adds	r7, r7, #20
 239              	.LCFI7:
 240              		.cfi_def_cfa_offset 4
 241 00c4 BD46     		mov	sp, r7
 242              	.LCFI8:
 243              		.cfi_def_cfa_register 13
 244              		@ sp needed
 245 00c6 5DF8047B 		ldr	r7, [sp], #4
 246              	.LCFI9:
 247              		.cfi_restore 7
 248              		.cfi_def_cfa_offset 0
 249 00ca 7047     		bx	lr
 250              	.L13:
 251              		.align	2
 252              	.L12:
 253 00cc 00100240 		.word	1073876992
 254 00d0 00000000 		.word	SystemCoreClock
 255 00d4 00127A00 		.word	8000000
 256 00d8 00093D00 		.word	4000000
 257 00dc 00000000 		.word	AHBPrescTable
 258              		.cfi_endproc
 259              	.LFE131:
 261              		.text
 262              	.Letext0:
 263              		.file 2 "d:\\arm-gcc\\arm-none-eabi\\include\\machine\\_default_types.h"
 264              		.file 3 "d:\\arm-gcc\\arm-none-eabi\\include\\sys\\_stdint.h"
 265              		.file 4 "Drivers/CMSIS/Include/core_cm4.h"
 266              		.file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h"
 267              		.file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s 			page 11


DEFINED SYMBOLS
                            *ABS*:00000000 system_stm32f3xx.c
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:24     .data.SystemCoreClock:00000000 SystemCoreClock
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:21     .data.SystemCoreClock:00000000 $d
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:31     .rodata.AHBPrescTable:00000000 AHBPrescTable
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:28     .rodata.AHBPrescTable:00000000 $d
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:39     .rodata.APBPrescTable:00000000 APBPrescTable
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:36     .rodata.APBPrescTable:00000000 $d
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:42     .text.SystemInit:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:48     .text.SystemInit:00000000 SystemInit
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:83     .text.SystemInit:00000020 $d
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:88     .text.SystemCoreClockUpdate:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:94     .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
C:\Users\zl835\AppData\Local\Temp\ccMZGmq8.s:253    .text.SystemCoreClockUpdate:000000cc $d

NO UNDEFINED SYMBOLS