V9_PMU302/build/stm32f3xx_hal_pwr.lst

ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 1


   1              		.cpu cortex-m4
   2              		.arch armv7e-m
   3              		.fpu fpv4-sp-d16
   4              		.eabi_attribute 27, 1
   5              		.eabi_attribute 28, 1
   6              		.eabi_attribute 20, 1
   7              		.eabi_attribute 21, 1
   8              		.eabi_attribute 23, 3
   9              		.eabi_attribute 24, 1
  10              		.eabi_attribute 25, 1
  11              		.eabi_attribute 26, 1
  12              		.eabi_attribute 30, 6
  13              		.eabi_attribute 34, 1
  14              		.eabi_attribute 18, 4
  15              		.file	"stm32f3xx_hal_pwr.c"
  16              		.text
  17              	.Ltext0:
  18              		.cfi_sections	.debug_frame
  19              		.section	.text.HAL_PWR_DeInit,"ax",%progbits
  20              		.align	1
  21              		.global	HAL_PWR_DeInit
  22              		.syntax unified
  23              		.thumb
  24              		.thumb_func
  26              	HAL_PWR_DeInit:
  27              	.LFB130:
  28              		.file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c"
   1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
   2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   ******************************************************************************
   3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @file    stm32f3xx_hal_pwr.c
   4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @author  MCD Application Team
   5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief   PWR HAL module driver.
   6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *          This file provides firmware functions to manage the following
   7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *          functionalities of the Power Controller (PWR) peripheral:
   8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *           + Initialization/de-initialization functions
   9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *           + Peripheral Control functions
  10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *
  11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   ******************************************************************************
  12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @attention
  13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *
  14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * Copyright (c) 2016 STMicroelectronics.
  15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * All rights reserved.
  16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *
  17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * This software is licensed under terms that can be found in the LICENSE file
  18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * in the root directory of this software component.
  19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *
  21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   ******************************************************************************
  22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
  23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
  24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
  25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #include "stm32f3xx_hal.h"
  26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
  27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @addtogroup STM32F3xx_HAL_Driver
  28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @{
  29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
  30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 2


  31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR PWR
  32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief PWR HAL module driver
  33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @{
  34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
  35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
  36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
  37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
  38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
  39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
  40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
  41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
  42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
  43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/
  44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
  45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
  46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @{
  47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
  48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
  49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
  50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *  @brief    Initialization and de-initialization functions
  51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *
  52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
  53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****  ===============================================================================
  54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****               ##### Initialization and de-initialization functions #####
  55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****  ===============================================================================
  56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     [..]
  57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       After reset, the backup domain (RTC registers, RTC backup data
  58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       registers and backup SRAM) is protected against possible unwanted
  59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       write accesses.
  60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       To enable access to the RTC Domain and RTC registers, proceed as follows:
  61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****         (+) Enable the Power Controller (PWR) APB1 interface clock using the
  62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****             __HAL_RCC_PWR_CLK_ENABLE() macro.
  63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****         (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
  64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
  65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
  66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @{
  67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
  68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
  69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
  70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Deinitializes the PWR peripheral registers to their default reset values.
  71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
  72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
  73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
  74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
  29              		.loc 1 74 1
  30              		.cfi_startproc
  31              		@ args = 0, pretend = 0, frame = 0
  32              		@ frame_needed = 1, uses_anonymous_args = 0
  33              		@ link register save eliminated.
  34 0000 80B4     		push	{r7}
  35              	.LCFI0:
  36              		.cfi_def_cfa_offset 4
  37              		.cfi_offset 7, -4
  38 0002 00AF     		add	r7, sp, #0
  39              	.LCFI1:
  40              		.cfi_def_cfa_register 7
  75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   __HAL_RCC_PWR_FORCE_RESET();
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 3


  41              		.loc 1 75 3
  42 0004 084B     		ldr	r3, .L2
  43 0006 1B69     		ldr	r3, [r3, #16]
  44 0008 074A     		ldr	r2, .L2
  45 000a 43F08053 		orr	r3, r3, #268435456
  46 000e 1361     		str	r3, [r2, #16]
  76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   __HAL_RCC_PWR_RELEASE_RESET();
  47              		.loc 1 76 3
  48 0010 054B     		ldr	r3, .L2
  49 0012 1B69     		ldr	r3, [r3, #16]
  50 0014 044A     		ldr	r2, .L2
  51 0016 23F08053 		bic	r3, r3, #268435456
  52 001a 1361     		str	r3, [r2, #16]
  77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
  53              		.loc 1 77 1
  54 001c 00BF     		nop
  55 001e BD46     		mov	sp, r7
  56              	.LCFI2:
  57              		.cfi_def_cfa_register 13
  58              		@ sp needed
  59 0020 5DF8047B 		ldr	r7, [sp], #4
  60              	.LCFI3:
  61              		.cfi_restore 7
  62              		.cfi_def_cfa_offset 0
  63 0024 7047     		bx	lr
  64              	.L3:
  65 0026 00BF     		.align	2
  66              	.L2:
  67 0028 00100240 		.word	1073876992
  68              		.cfi_endproc
  69              	.LFE130:
  71              		.section	.text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
  72              		.align	1
  73              		.global	HAL_PWR_EnableBkUpAccess
  74              		.syntax unified
  75              		.thumb
  76              		.thumb_func
  78              	HAL_PWR_EnableBkUpAccess:
  79              	.LFB131:
  78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
  79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
  80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Enables access to the backup domain (RTC registers, RTC
  81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *         backup data registers and backup SRAM).
  82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note  If the HSE divided by 32 is used as the RTC clock, the
  83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *         Backup Domain Access should be kept enabled.
  84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
  85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
  86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
  87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
  80              		.loc 1 87 1
  81              		.cfi_startproc
  82              		@ args = 0, pretend = 0, frame = 0
  83              		@ frame_needed = 1, uses_anonymous_args = 0
  84              		@ link register save eliminated.
  85 0000 80B4     		push	{r7}
  86              	.LCFI4:
  87              		.cfi_def_cfa_offset 4
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 4


  88              		.cfi_offset 7, -4
  89 0002 00AF     		add	r7, sp, #0
  90              	.LCFI5:
  91              		.cfi_def_cfa_register 7
  88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   SET_BIT(PWR->CR, PWR_CR_DBP);  
  92              		.loc 1 88 3
  93 0004 054B     		ldr	r3, .L5
  94 0006 1B68     		ldr	r3, [r3]
  95 0008 044A     		ldr	r2, .L5
  96 000a 43F48073 		orr	r3, r3, #256
  97 000e 1360     		str	r3, [r2]
  89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
  98              		.loc 1 89 1
  99 0010 00BF     		nop
 100 0012 BD46     		mov	sp, r7
 101              	.LCFI6:
 102              		.cfi_def_cfa_register 13
 103              		@ sp needed
 104 0014 5DF8047B 		ldr	r7, [sp], #4
 105              	.LCFI7:
 106              		.cfi_restore 7
 107              		.cfi_def_cfa_offset 0
 108 0018 7047     		bx	lr
 109              	.L6:
 110 001a 00BF     		.align	2
 111              	.L5:
 112 001c 00700040 		.word	1073770496
 113              		.cfi_endproc
 114              	.LFE131:
 116              		.section	.text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
 117              		.align	1
 118              		.global	HAL_PWR_DisableBkUpAccess
 119              		.syntax unified
 120              		.thumb
 121              		.thumb_func
 123              	HAL_PWR_DisableBkUpAccess:
 124              	.LFB132:
  90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
  91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
  92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Disables access to the backup domain (RTC registers, RTC
  93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *         backup data registers and backup SRAM).
  94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note  If the HSE divided by 32 is used as the RTC clock, the
  95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *         Backup Domain Access should be kept enabled.
  96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
  97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
  98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
  99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
 125              		.loc 1 99 1
 126              		.cfi_startproc
 127              		@ args = 0, pretend = 0, frame = 0
 128              		@ frame_needed = 1, uses_anonymous_args = 0
 129              		@ link register save eliminated.
 130 0000 80B4     		push	{r7}
 131              	.LCFI8:
 132              		.cfi_def_cfa_offset 4
 133              		.cfi_offset 7, -4
 134 0002 00AF     		add	r7, sp, #0
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 5


 135              	.LCFI9:
 136              		.cfi_def_cfa_register 7
 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   CLEAR_BIT(PWR->CR, PWR_CR_DBP);  
 137              		.loc 1 100 3
 138 0004 054B     		ldr	r3, .L8
 139 0006 1B68     		ldr	r3, [r3]
 140 0008 044A     		ldr	r2, .L8
 141 000a 23F48073 		bic	r3, r3, #256
 142 000e 1360     		str	r3, [r2]
 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
 143              		.loc 1 101 1
 144 0010 00BF     		nop
 145 0012 BD46     		mov	sp, r7
 146              	.LCFI10:
 147              		.cfi_def_cfa_register 13
 148              		@ sp needed
 149 0014 5DF8047B 		ldr	r7, [sp], #4
 150              	.LCFI11:
 151              		.cfi_restore 7
 152              		.cfi_def_cfa_offset 0
 153 0018 7047     		bx	lr
 154              	.L9:
 155 001a 00BF     		.align	2
 156              	.L8:
 157 001c 00700040 		.word	1073770496
 158              		.cfi_endproc
 159              	.LFE132:
 161              		.section	.rodata
 162              		.align	2
 163              	.LC0:
 164 0000 44726976 		.ascii	"Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr."
 164      6572732F 
 164      53544D33 
 164      32463378 
 164      785F4841 
 165 0033 6300     		.ascii	"c\000"
 166              		.section	.text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
 167              		.align	1
 168              		.global	HAL_PWR_EnableWakeUpPin
 169              		.syntax unified
 170              		.thumb
 171              		.thumb_func
 173              	HAL_PWR_EnableWakeUpPin:
 174              	.LFB133:
 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @}
 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 
 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *  @brief Low Power modes configuration functions
 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *
 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****  ===============================================================================
 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****                  ##### Peripheral Control functions #####
 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****  ===============================================================================
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 6


 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     
 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     *** WakeUp pin configuration ***
 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     ================================
 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     [..]
 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           forced in input pull down configuration and is active on rising edges.
 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) There are up to three WakeUp pins:
 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++)WakeUp Pin 1 on PA.00.
 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++)WakeUp Pin 3 on PE.06.
 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     *** Main and Backup Regulators configuration ***
 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     ================================================
 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     [..]
 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           the backup SRAM is powered from VDD which replaces the VBAT power supply to
 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           save battery life.
 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) The backup SRAM is not mass erased by a tamper event. It is read
 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           protected to prevent confidential data, such as cryptographic private
 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           key, from being accessed. The backup SRAM can be erased only through
 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           the Flash interface when a protection level change from level 1 to
 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           level 0 is requested.
 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       -@- Refer to the description of Read protection (RDP) in the Flash
 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           programming manual.
 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****         Refer to the datasheets for more details.
 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     *** Low Power modes configuration ***
 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     =====================================
 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     [..]
 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       The devices feature 3 low-power modes:
 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) Stop mode: all clocks are stopped, regulator running, regulator
 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           in low power mode
 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****    *** Sleep mode ***
 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****    ==================
 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     [..]
 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) Entry:
 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S
 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****               functions with
 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****      
 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) Exit:
 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****               controller (NVIC) can wake up the device from Sleep mode.
 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****    *** Stop mode ***
 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****    =================
 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     [..]
 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       and the HSE RC oscillators are disabled. Internal SRAM and register contents
 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       are preserved.
 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       The voltage regulator can be configured either in normal or low-power mode to minimize the co
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 7


 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) Entry:
 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPEN
 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****              function with:
 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++) Main regulator ON or
 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++) Low Power regulator ON.
 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) Exit:
 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, 
 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****                when programmed in wakeup mode (the peripheral must be 
 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****                programmed in wakeup mode and the corresponding interrupt vector 
 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****                must be enabled in the NVIC).
 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****    *** Standby mode ***
 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****    ====================
 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****      [..]
 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       The Standby mode allows to achieve the lowest power consumption. It is based
 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       the HSE oscillator are also switched off. SRAM and register contents are lost
 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       except for the RTC registers, RTC backup registers, backup SRAM and Standby
 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       circuitry.
 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       The voltage regulator is OFF.
 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) Entry:
 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (+) Exit:
 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****           (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****                tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****    *** Auto-wakeup (AWU) from low-power mode ***
 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****    =============================================
 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     [..]
 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       without depending on an external interrupt (Auto-wakeup mode).
 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****            is necessary to configure the RTC to detect the tamper or time stamp event using the
 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****            HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****            configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT()
 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     (+) Comparator auto-wakeup (AWU) from the Stop mode
 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****       (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****            (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for c
 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****                  to be sensitive to to the selected edges (falling, rising or falling 
 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****                  and rising) (Interrupt or Event modes) using the EXTI_Init() function.
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 8


 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****            (+++) Configure the comparator to generate the event.      
 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @{
 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Enables the WakeUp PINx functionality.
 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *         This parameter can be value of :
 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *           @ref PWR_WakeUp_Pins
 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
 175              		.loc 1 242 1
 176              		.cfi_startproc
 177              		@ args = 0, pretend = 0, frame = 8
 178              		@ frame_needed = 1, uses_anonymous_args = 0
 179 0000 80B5     		push	{r7, lr}
 180              	.LCFI12:
 181              		.cfi_def_cfa_offset 8
 182              		.cfi_offset 7, -8
 183              		.cfi_offset 14, -4
 184 0002 82B0     		sub	sp, sp, #8
 185              	.LCFI13:
 186              		.cfi_def_cfa_offset 16
 187 0004 00AF     		add	r7, sp, #0
 188              	.LCFI14:
 189              		.cfi_def_cfa_register 7
 190 0006 7860     		str	r0, [r7, #4]
 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Check the parameters */
 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
 191              		.loc 1 244 3
 192 0008 7B68     		ldr	r3, [r7, #4]
 193 000a B3F5807F 		cmp	r3, #256
 194 000e 0BD0     		beq	.L11
 195              		.loc 1 244 3 is_stmt 0 discriminator 1
 196 0010 7B68     		ldr	r3, [r7, #4]
 197 0012 B3F5007F 		cmp	r3, #512
 198 0016 07D0     		beq	.L11
 199              		.loc 1 244 3 discriminator 2
 200 0018 7B68     		ldr	r3, [r7, #4]
 201 001a B3F5806F 		cmp	r3, #1024
 202 001e 03D0     		beq	.L11
 203              		.loc 1 244 3 discriminator 3
 204 0020 F421     		movs	r1, #244
 205 0022 0648     		ldr	r0, .L12
 206 0024 FFF7FEFF 		bl	assert_failed
 207              	.L11:
 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Enable the EWUPx pin */
 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   SET_BIT(PWR->CSR, WakeUpPinx);
 208              		.loc 1 246 3 is_stmt 1
 209 0028 054B     		ldr	r3, .L12+4
 210 002a 5A68     		ldr	r2, [r3, #4]
 211 002c 0449     		ldr	r1, .L12+4
 212 002e 7B68     		ldr	r3, [r7, #4]
 213 0030 1343     		orrs	r3, r3, r2
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 9


 214 0032 4B60     		str	r3, [r1, #4]
 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
 215              		.loc 1 247 1
 216 0034 00BF     		nop
 217 0036 0837     		adds	r7, r7, #8
 218              	.LCFI15:
 219              		.cfi_def_cfa_offset 8
 220 0038 BD46     		mov	sp, r7
 221              	.LCFI16:
 222              		.cfi_def_cfa_register 13
 223              		@ sp needed
 224 003a 80BD     		pop	{r7, pc}
 225              	.L13:
 226              		.align	2
 227              	.L12:
 228 003c 00000000 		.word	.LC0
 229 0040 00700040 		.word	1073770496
 230              		.cfi_endproc
 231              	.LFE133:
 233              		.section	.text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
 234              		.align	1
 235              		.global	HAL_PWR_DisableWakeUpPin
 236              		.syntax unified
 237              		.thumb
 238              		.thumb_func
 240              	HAL_PWR_DisableWakeUpPin:
 241              	.LFB134:
 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Disables the WakeUp PINx functionality.
 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *         This parameter can be values of :
 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *           @ref PWR_WakeUp_Pins
 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
 242              		.loc 1 257 1
 243              		.cfi_startproc
 244              		@ args = 0, pretend = 0, frame = 8
 245              		@ frame_needed = 1, uses_anonymous_args = 0
 246 0000 80B5     		push	{r7, lr}
 247              	.LCFI17:
 248              		.cfi_def_cfa_offset 8
 249              		.cfi_offset 7, -8
 250              		.cfi_offset 14, -4
 251 0002 82B0     		sub	sp, sp, #8
 252              	.LCFI18:
 253              		.cfi_def_cfa_offset 16
 254 0004 00AF     		add	r7, sp, #0
 255              	.LCFI19:
 256              		.cfi_def_cfa_register 7
 257 0006 7860     		str	r0, [r7, #4]
 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Check the parameters */
 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
 258              		.loc 1 259 3
 259 0008 7B68     		ldr	r3, [r7, #4]
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 10


 260 000a B3F5807F 		cmp	r3, #256
 261 000e 0CD0     		beq	.L15
 262              		.loc 1 259 3 is_stmt 0 discriminator 1
 263 0010 7B68     		ldr	r3, [r7, #4]
 264 0012 B3F5007F 		cmp	r3, #512
 265 0016 08D0     		beq	.L15
 266              		.loc 1 259 3 discriminator 2
 267 0018 7B68     		ldr	r3, [r7, #4]
 268 001a B3F5806F 		cmp	r3, #1024
 269 001e 04D0     		beq	.L15
 270              		.loc 1 259 3 discriminator 3
 271 0020 40F20311 		movw	r1, #259
 272 0024 0648     		ldr	r0, .L16
 273 0026 FFF7FEFF 		bl	assert_failed
 274              	.L15:
 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Disable the EWUPx pin */
 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   CLEAR_BIT(PWR->CSR, WakeUpPinx);
 275              		.loc 1 261 3 is_stmt 1
 276 002a 064B     		ldr	r3, .L16+4
 277 002c 5A68     		ldr	r2, [r3, #4]
 278 002e 7B68     		ldr	r3, [r7, #4]
 279 0030 DB43     		mvns	r3, r3
 280 0032 0449     		ldr	r1, .L16+4
 281 0034 1340     		ands	r3, r3, r2
 282 0036 4B60     		str	r3, [r1, #4]
 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
 283              		.loc 1 262 1
 284 0038 00BF     		nop
 285 003a 0837     		adds	r7, r7, #8
 286              	.LCFI20:
 287              		.cfi_def_cfa_offset 8
 288 003c BD46     		mov	sp, r7
 289              	.LCFI21:
 290              		.cfi_def_cfa_register 13
 291              		@ sp needed
 292 003e 80BD     		pop	{r7, pc}
 293              	.L17:
 294              		.align	2
 295              	.L16:
 296 0040 00000000 		.word	.LC0
 297 0044 00700040 		.word	1073770496
 298              		.cfi_endproc
 299              	.LFE134:
 301              		.section	.text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
 302              		.align	1
 303              		.global	HAL_PWR_EnterSLEEPMode
 304              		.syntax unified
 305              		.thumb
 306              		.thumb_func
 308              	HAL_PWR_EnterSLEEPMode:
 309              	.LFB135:
 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Enters Sleep mode.
 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @param Regulator Specifies the regulator state in SLEEP mode.
 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *          This parameter can be one of the following values:
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 11


 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note This parameter has no effect in F3 family and is just maintained to 
 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *       offer full portability of other STM32 families software.
 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *           When WFI entry is used, tick interrupt have to be disabled if not desired as 
 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *           the interrupt wake up source.
 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *           This parameter can be one of the following values:
 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
 310              		.loc 1 282 1
 311              		.cfi_startproc
 312              		@ args = 0, pretend = 0, frame = 8
 313              		@ frame_needed = 1, uses_anonymous_args = 0
 314 0000 80B5     		push	{r7, lr}
 315              	.LCFI22:
 316              		.cfi_def_cfa_offset 8
 317              		.cfi_offset 7, -8
 318              		.cfi_offset 14, -4
 319 0002 82B0     		sub	sp, sp, #8
 320              	.LCFI23:
 321              		.cfi_def_cfa_offset 16
 322 0004 00AF     		add	r7, sp, #0
 323              	.LCFI24:
 324              		.cfi_def_cfa_register 7
 325 0006 7860     		str	r0, [r7, #4]
 326 0008 0B46     		mov	r3, r1
 327 000a FB70     		strb	r3, [r7, #3]
 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Check the parameters */
 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
 328              		.loc 1 284 3
 329 000c FB78     		ldrb	r3, [r7, #3]	@ zero_extendqisi2
 330 000e 012B     		cmp	r3, #1
 331 0010 07D0     		beq	.L19
 332              		.loc 1 284 3 is_stmt 0 discriminator 1
 333 0012 FB78     		ldrb	r3, [r7, #3]	@ zero_extendqisi2
 334 0014 022B     		cmp	r3, #2
 335 0016 04D0     		beq	.L19
 336              		.loc 1 284 3 discriminator 2
 337 0018 4FF48E71 		mov	r1, #284
 338 001c 0A48     		ldr	r0, .L23
 339 001e FFF7FEFF 		bl	assert_failed
 340              	.L19:
 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Prevent unused argument(s) compilation warning */
 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   UNUSED(Regulator);
 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Clear SLEEPDEEP bit of Cortex System Control Register */
 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 341              		.loc 1 290 12 is_stmt 1
 342 0022 0A4B     		ldr	r3, .L23+4
 343 0024 1B69     		ldr	r3, [r3, #16]
 344 0026 094A     		ldr	r2, .L23+4
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 12


 345 0028 23F00403 		bic	r3, r3, #4
 346 002c 1361     		str	r3, [r2, #16]
 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Select SLEEP mode entry -------------------------------------------------*/
 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
 347              		.loc 1 293 5
 348 002e FB78     		ldrb	r3, [r7, #3]	@ zero_extendqisi2
 349 0030 012B     		cmp	r3, #1
 350 0032 01D1     		bne	.L20
 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   {
 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     /* Request Wait For Interrupt */
 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     __WFI();
 351              		.loc 1 296 5
 352              		.syntax unified
 353              	@ 296 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
 354 0034 30BF     		wfi
 355              	@ 0 "" 2
 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   }
 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   else
 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   {
 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     /* Request Wait For Event */
 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     __SEV();
 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     __WFE();
 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     __WFE();
 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   }
 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
 356              		.loc 1 305 1
 357              		.thumb
 358              		.syntax unified
 359 0036 02E0     		b	.L22
 360              	.L20:
 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     __WFE();
 361              		.loc 1 301 5
 362              		.syntax unified
 363              	@ 301 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
 364 0038 40BF     		sev
 365              	@ 0 "" 2
 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     __WFE();
 366              		.loc 1 302 5
 367              	@ 302 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
 368 003a 20BF     		wfe
 369              	@ 0 "" 2
 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   }
 370              		.loc 1 303 5
 371              	@ 303 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
 372 003c 20BF     		wfe
 373              	@ 0 "" 2
 374              		.thumb
 375              		.syntax unified
 376              	.L22:
 377              		.loc 1 305 1
 378 003e 00BF     		nop
 379 0040 0837     		adds	r7, r7, #8
 380              	.LCFI25:
 381              		.cfi_def_cfa_offset 8
 382 0042 BD46     		mov	sp, r7
 383              	.LCFI26:
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 13


 384              		.cfi_def_cfa_register 13
 385              		@ sp needed
 386 0044 80BD     		pop	{r7, pc}
 387              	.L24:
 388 0046 00BF     		.align	2
 389              	.L23:
 390 0048 00000000 		.word	.LC0
 391 004c 00ED00E0 		.word	-536810240
 392              		.cfi_endproc
 393              	.LFE135:
 395              		.section	.text.HAL_PWR_EnterSTOPMode,"ax",%progbits
 396              		.align	1
 397              		.global	HAL_PWR_EnterSTOPMode
 398              		.syntax unified
 399              		.thumb
 400              		.thumb_func
 402              	HAL_PWR_EnterSTOPMode:
 403              	.LFB136:
 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Enters STOP mode.
 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note  When exiting Stop mode by issuing an interrupt or a wakeup event,
 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *         the HSI RC oscillator is selected as system clock.
 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note  When the voltage regulator operates in low power mode, an additional
 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *         startup delay is incurred when waking up from Stop mode.
 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *         By keeping the internal regulator ON during Stop mode, the consumption
 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *         is higher although the startup time is reduced.
 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @param Regulator Specifies the regulator state in STOP mode.
 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *          This parameter can be one of the following values:
 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *            @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *            @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *          This parameter can be one of the following values:
 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *            @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *            @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
 404              		.loc 1 327 1
 405              		.cfi_startproc
 406              		@ args = 0, pretend = 0, frame = 16
 407              		@ frame_needed = 1, uses_anonymous_args = 0
 408 0000 80B5     		push	{r7, lr}
 409              	.LCFI27:
 410              		.cfi_def_cfa_offset 8
 411              		.cfi_offset 7, -8
 412              		.cfi_offset 14, -4
 413 0002 84B0     		sub	sp, sp, #16
 414              	.LCFI28:
 415              		.cfi_def_cfa_offset 24
 416 0004 00AF     		add	r7, sp, #0
 417              	.LCFI29:
 418              		.cfi_def_cfa_register 7
 419 0006 7860     		str	r0, [r7, #4]
 420 0008 0B46     		mov	r3, r1
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 14


 421 000a FB70     		strb	r3, [r7, #3]
 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   uint32_t tmpreg = 0U;
 422              		.loc 1 328 12
 423 000c 0023     		movs	r3, #0
 424 000e FB60     		str	r3, [r7, #12]
 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Check the parameters */
 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   assert_param(IS_PWR_REGULATOR(Regulator));
 425              		.loc 1 331 3
 426 0010 7B68     		ldr	r3, [r7, #4]
 427 0012 002B     		cmp	r3, #0
 428 0014 07D0     		beq	.L26
 429              		.loc 1 331 3 is_stmt 0 discriminator 1
 430 0016 7B68     		ldr	r3, [r7, #4]
 431 0018 012B     		cmp	r3, #1
 432 001a 04D0     		beq	.L26
 433              		.loc 1 331 3 discriminator 2
 434 001c 40F24B11 		movw	r1, #331
 435 0020 1948     		ldr	r0, .L30
 436 0022 FFF7FEFF 		bl	assert_failed
 437              	.L26:
 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
 438              		.loc 1 332 3 is_stmt 1
 439 0026 FB78     		ldrb	r3, [r7, #3]	@ zero_extendqisi2
 440 0028 012B     		cmp	r3, #1
 441 002a 07D0     		beq	.L27
 442              		.loc 1 332 3 is_stmt 0 discriminator 1
 443 002c FB78     		ldrb	r3, [r7, #3]	@ zero_extendqisi2
 444 002e 022B     		cmp	r3, #2
 445 0030 04D0     		beq	.L27
 446              		.loc 1 332 3 discriminator 2
 447 0032 4FF4A671 		mov	r1, #332
 448 0036 1448     		ldr	r0, .L30
 449 0038 FFF7FEFF 		bl	assert_failed
 450              	.L27:
 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Select the regulator state in STOP mode ---------------------------------*/
 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   tmpreg = PWR->CR;
 451              		.loc 1 335 15 is_stmt 1
 452 003c 134B     		ldr	r3, .L30+4
 453              		.loc 1 335 10
 454 003e 1B68     		ldr	r3, [r3]
 455 0040 FB60     		str	r3, [r7, #12]
 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   
 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Clear PDDS and LPDS bits */
 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
 456              		.loc 1 338 10
 457 0042 FB68     		ldr	r3, [r7, #12]
 458 0044 23F00303 		bic	r3, r3, #3
 459 0048 FB60     		str	r3, [r7, #12]
 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Set LPDS bit according to Regulator value */
 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   tmpreg |= Regulator;
 460              		.loc 1 341 10
 461 004a FA68     		ldr	r2, [r7, #12]
 462 004c 7B68     		ldr	r3, [r7, #4]
 463 004e 1343     		orrs	r3, r3, r2
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 15


 464 0050 FB60     		str	r3, [r7, #12]
 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Store the new value */
 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   PWR->CR = tmpreg;
 465              		.loc 1 344 6
 466 0052 0E4A     		ldr	r2, .L30+4
 467              		.loc 1 344 11
 468 0054 FB68     		ldr	r3, [r7, #12]
 469 0056 1360     		str	r3, [r2]
 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 470              		.loc 1 347 12
 471 0058 0D4B     		ldr	r3, .L30+8
 472 005a 1B69     		ldr	r3, [r3, #16]
 473 005c 0C4A     		ldr	r2, .L30+8
 474 005e 43F00403 		orr	r3, r3, #4
 475 0062 1361     		str	r3, [r2, #16]
 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   if(STOPEntry == PWR_STOPENTRY_WFI)
 476              		.loc 1 350 5
 477 0064 FB78     		ldrb	r3, [r7, #3]	@ zero_extendqisi2
 478 0066 012B     		cmp	r3, #1
 479 0068 01D1     		bne	.L28
 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   {
 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     /* Request Wait For Interrupt */
 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     __WFI();
 480              		.loc 1 353 5
 481              		.syntax unified
 482              	@ 353 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
 483 006a 30BF     		wfi
 484              	@ 0 "" 2
 485              		.thumb
 486              		.syntax unified
 487 006c 02E0     		b	.L29
 488              	.L28:
 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   }
 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   else
 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   {
 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     /* Request Wait For Event */
 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     __SEV();
 489              		.loc 1 358 5
 490              		.syntax unified
 491              	@ 358 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
 492 006e 40BF     		sev
 493              	@ 0 "" 2
 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     __WFE();
 494              		.loc 1 359 5
 495              	@ 359 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
 496 0070 20BF     		wfe
 497              	@ 0 "" 2
 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****     __WFE();
 498              		.loc 1 360 5
 499              	@ 360 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
 500 0072 20BF     		wfe
 501              	@ 0 "" 2
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 16


 502              		.thumb
 503              		.syntax unified
 504              	.L29:
 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   }
 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 505              		.loc 1 364 12
 506 0074 064B     		ldr	r3, .L30+8
 507 0076 1B69     		ldr	r3, [r3, #16]
 508 0078 054A     		ldr	r2, .L30+8
 509 007a 23F00403 		bic	r3, r3, #4
 510 007e 1361     		str	r3, [r2, #16]
 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
 511              		.loc 1 365 1
 512 0080 00BF     		nop
 513 0082 1037     		adds	r7, r7, #16
 514              	.LCFI30:
 515              		.cfi_def_cfa_offset 8
 516 0084 BD46     		mov	sp, r7
 517              	.LCFI31:
 518              		.cfi_def_cfa_register 13
 519              		@ sp needed
 520 0086 80BD     		pop	{r7, pc}
 521              	.L31:
 522              		.align	2
 523              	.L30:
 524 0088 00000000 		.word	.LC0
 525 008c 00700040 		.word	1073770496
 526 0090 00ED00E0 		.word	-536810240
 527              		.cfi_endproc
 528              	.LFE136:
 530              		.section	.text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
 531              		.align	1
 532              		.global	HAL_PWR_EnterSTANDBYMode
 533              		.syntax unified
 534              		.thumb
 535              		.thumb_func
 537              	HAL_PWR_EnterSTANDBYMode:
 538              	.LFB137:
 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Enters STANDBY mode.
 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note  In Standby mode, all I/O pins are high impedance except for:
 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *          - Reset pad (still available), 
 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *          - RTC alternate function pins if configured for tamper, time-stamp, RTC
 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *            Alarm out, or RTC clock calibration out, 
 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *          - WKUP pins if enabled.
 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
 539              		.loc 1 377 1
 540              		.cfi_startproc
 541              		@ args = 0, pretend = 0, frame = 0
 542              		@ frame_needed = 1, uses_anonymous_args = 0
 543              		@ link register save eliminated.
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 17


 544 0000 80B4     		push	{r7}
 545              	.LCFI32:
 546              		.cfi_def_cfa_offset 4
 547              		.cfi_offset 7, -4
 548 0002 00AF     		add	r7, sp, #0
 549              	.LCFI33:
 550              		.cfi_def_cfa_register 7
 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Select STANDBY mode */
 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   PWR->CR |= PWR_CR_PDDS;
 551              		.loc 1 379 11
 552 0004 084B     		ldr	r3, .L33
 553 0006 1B68     		ldr	r3, [r3]
 554 0008 074A     		ldr	r2, .L33
 555 000a 43F00203 		orr	r3, r3, #2
 556 000e 1360     		str	r3, [r2]
 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 557              		.loc 1 382 12
 558 0010 064B     		ldr	r3, .L33+4
 559 0012 1B69     		ldr	r3, [r3, #16]
 560 0014 054A     		ldr	r2, .L33+4
 561 0016 43F00403 		orr	r3, r3, #4
 562 001a 1361     		str	r3, [r2, #16]
 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* This option is used to ensure that store operations are completed */
 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #if defined ( __CC_ARM)
 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   __force_stores();
 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #endif
 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Request Wait For Interrupt */
 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   __WFI();
 563              		.loc 1 389 3
 564              		.syntax unified
 565              	@ 389 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
 566 001c 30BF     		wfi
 567              	@ 0 "" 2
 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
 568              		.loc 1 390 1
 569              		.thumb
 570              		.syntax unified
 571 001e 00BF     		nop
 572 0020 BD46     		mov	sp, r7
 573              	.LCFI34:
 574              		.cfi_def_cfa_register 13
 575              		@ sp needed
 576 0022 5DF8047B 		ldr	r7, [sp], #4
 577              	.LCFI35:
 578              		.cfi_restore 7
 579              		.cfi_def_cfa_offset 0
 580 0026 7047     		bx	lr
 581              	.L34:
 582              		.align	2
 583              	.L33:
 584 0028 00700040 		.word	1073770496
 585 002c 00ED00E0 		.word	-536810240
 586              		.cfi_endproc
 587              	.LFE137:
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 18


 589              		.section	.text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
 590              		.align	1
 591              		.global	HAL_PWR_EnableSleepOnExit
 592              		.syntax unified
 593              		.thumb
 594              		.thumb_func
 596              	HAL_PWR_EnableSleepOnExit:
 597              	.LFB138:
 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *       re-enters SLEEP mode when an interruption handling is over.
 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *       Setting this bit is useful when the processor is expected to run only on
 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *       interruptions handling.         
 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
 598              		.loc 1 401 1
 599              		.cfi_startproc
 600              		@ args = 0, pretend = 0, frame = 0
 601              		@ frame_needed = 1, uses_anonymous_args = 0
 602              		@ link register save eliminated.
 603 0000 80B4     		push	{r7}
 604              	.LCFI36:
 605              		.cfi_def_cfa_offset 4
 606              		.cfi_offset 7, -4
 607 0002 00AF     		add	r7, sp, #0
 608              	.LCFI37:
 609              		.cfi_def_cfa_register 7
 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Set SLEEPONEXIT bit of Cortex System Control Register */
 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 610              		.loc 1 403 3
 611 0004 054B     		ldr	r3, .L36
 612 0006 1B69     		ldr	r3, [r3, #16]
 613 0008 044A     		ldr	r2, .L36
 614 000a 43F00203 		orr	r3, r3, #2
 615 000e 1361     		str	r3, [r2, #16]
 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
 616              		.loc 1 404 1
 617 0010 00BF     		nop
 618 0012 BD46     		mov	sp, r7
 619              	.LCFI38:
 620              		.cfi_def_cfa_register 13
 621              		@ sp needed
 622 0014 5DF8047B 		ldr	r7, [sp], #4
 623              	.LCFI39:
 624              		.cfi_restore 7
 625              		.cfi_def_cfa_offset 0
 626 0018 7047     		bx	lr
 627              	.L37:
 628 001a 00BF     		.align	2
 629              	.L36:
 630 001c 00ED00E0 		.word	-536810240
 631              		.cfi_endproc
 632              	.LFE138:
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 19


 634              		.section	.text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
 635              		.align	1
 636              		.global	HAL_PWR_DisableSleepOnExit
 637              		.syntax unified
 638              		.thumb
 639              		.thumb_func
 641              	HAL_PWR_DisableSleepOnExit:
 642              	.LFB139:
 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *       re-enters SLEEP mode when an interruption handling is over.          
 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
 643              		.loc 1 414 1
 644              		.cfi_startproc
 645              		@ args = 0, pretend = 0, frame = 0
 646              		@ frame_needed = 1, uses_anonymous_args = 0
 647              		@ link register save eliminated.
 648 0000 80B4     		push	{r7}
 649              	.LCFI40:
 650              		.cfi_def_cfa_offset 4
 651              		.cfi_offset 7, -4
 652 0002 00AF     		add	r7, sp, #0
 653              	.LCFI41:
 654              		.cfi_def_cfa_register 7
 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 655              		.loc 1 416 3
 656 0004 054B     		ldr	r3, .L39
 657 0006 1B69     		ldr	r3, [r3, #16]
 658 0008 044A     		ldr	r2, .L39
 659 000a 23F00203 		bic	r3, r3, #2
 660 000e 1361     		str	r3, [r2, #16]
 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
 661              		.loc 1 417 1
 662 0010 00BF     		nop
 663 0012 BD46     		mov	sp, r7
 664              	.LCFI42:
 665              		.cfi_def_cfa_register 13
 666              		@ sp needed
 667 0014 5DF8047B 		ldr	r7, [sp], #4
 668              	.LCFI43:
 669              		.cfi_restore 7
 670              		.cfi_def_cfa_offset 0
 671 0018 7047     		bx	lr
 672              	.L40:
 673 001a 00BF     		.align	2
 674              	.L39:
 675 001c 00ED00E0 		.word	-536810240
 676              		.cfi_endproc
 677              	.LFE139:
 679              		.section	.text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 20


 680              		.align	1
 681              		.global	HAL_PWR_EnableSEVOnPend
 682              		.syntax unified
 683              		.thumb
 684              		.thumb_func
 686              	HAL_PWR_EnableSEVOnPend:
 687              	.LFB140:
 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Enables CORTEX M4 SEVONPEND bit. 
 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *       WFE to wake up when an interrupt moves from inactive to pended.
 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
 688              		.loc 1 428 1
 689              		.cfi_startproc
 690              		@ args = 0, pretend = 0, frame = 0
 691              		@ frame_needed = 1, uses_anonymous_args = 0
 692              		@ link register save eliminated.
 693 0000 80B4     		push	{r7}
 694              	.LCFI44:
 695              		.cfi_def_cfa_offset 4
 696              		.cfi_offset 7, -4
 697 0002 00AF     		add	r7, sp, #0
 698              	.LCFI45:
 699              		.cfi_def_cfa_register 7
 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Set SEVONPEND bit of Cortex System Control Register */
 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 700              		.loc 1 430 3
 701 0004 054B     		ldr	r3, .L42
 702 0006 1B69     		ldr	r3, [r3, #16]
 703 0008 044A     		ldr	r2, .L42
 704 000a 43F01003 		orr	r3, r3, #16
 705 000e 1361     		str	r3, [r2, #16]
 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
 706              		.loc 1 431 1
 707 0010 00BF     		nop
 708 0012 BD46     		mov	sp, r7
 709              	.LCFI46:
 710              		.cfi_def_cfa_register 13
 711              		@ sp needed
 712 0014 5DF8047B 		ldr	r7, [sp], #4
 713              	.LCFI47:
 714              		.cfi_restore 7
 715              		.cfi_def_cfa_offset 0
 716 0018 7047     		bx	lr
 717              	.L43:
 718 001a 00BF     		.align	2
 719              	.L42:
 720 001c 00ED00E0 		.word	-536810240
 721              		.cfi_endproc
 722              	.LFE140:
 724              		.section	.text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 21


 725              		.align	1
 726              		.global	HAL_PWR_DisableSEVOnPend
 727              		.syntax unified
 728              		.thumb
 729              		.thumb_func
 731              	HAL_PWR_DisableSEVOnPend:
 732              	.LFB141:
 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** 
 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @brief Disables CORTEX M4 SEVONPEND bit. 
 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   *       WFE to wake up when an interrupt moves from inactive to pended.         
 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   * @retval None
 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   */
 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
 733              		.loc 1 441 1
 734              		.cfi_startproc
 735              		@ args = 0, pretend = 0, frame = 0
 736              		@ frame_needed = 1, uses_anonymous_args = 0
 737              		@ link register save eliminated.
 738 0000 80B4     		push	{r7}
 739              	.LCFI48:
 740              		.cfi_def_cfa_offset 4
 741              		.cfi_offset 7, -4
 742 0002 00AF     		add	r7, sp, #0
 743              	.LCFI49:
 744              		.cfi_def_cfa_register 7
 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   /* Clear SEVONPEND bit of Cortex System Control Register */
 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 745              		.loc 1 443 3
 746 0004 054B     		ldr	r3, .L45
 747 0006 1B69     		ldr	r3, [r3, #16]
 748 0008 044A     		ldr	r2, .L45
 749 000a 23F01003 		bic	r3, r3, #16
 750 000e 1361     		str	r3, [r2, #16]
 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
 751              		.loc 1 444 1
 752 0010 00BF     		nop
 753 0012 BD46     		mov	sp, r7
 754              	.LCFI50:
 755              		.cfi_def_cfa_register 13
 756              		@ sp needed
 757 0014 5DF8047B 		ldr	r7, [sp], #4
 758              	.LCFI51:
 759              		.cfi_restore 7
 760              		.cfi_def_cfa_offset 0
 761 0018 7047     		bx	lr
 762              	.L46:
 763 001a 00BF     		.align	2
 764              	.L45:
 765 001c 00ED00E0 		.word	-536810240
 766              		.cfi_endproc
 767              	.LFE141:
 769              		.text
 770              	.Letext0:
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 22


 771              		.file 2 "d:\\arm-gcc\\arm-none-eabi\\include\\machine\\_default_types.h"
 772              		.file 3 "d:\\arm-gcc\\arm-none-eabi\\include\\sys\\_stdint.h"
 773              		.file 4 "Drivers/CMSIS/Include/core_cm4.h"
 774              		.file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h"
ARM GAS  C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s 			page 23


DEFINED SYMBOLS
                            *ABS*:00000000 stm32f3xx_hal_pwr.c
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:20     .text.HAL_PWR_DeInit:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:26     .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:67     .text.HAL_PWR_DeInit:00000028 $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:72     .text.HAL_PWR_EnableBkUpAccess:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:78     .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:112    .text.HAL_PWR_EnableBkUpAccess:0000001c $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:117    .text.HAL_PWR_DisableBkUpAccess:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:123    .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:157    .text.HAL_PWR_DisableBkUpAccess:0000001c $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:162    .rodata:00000000 $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:167    .text.HAL_PWR_EnableWakeUpPin:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:173    .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:228    .text.HAL_PWR_EnableWakeUpPin:0000003c $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:234    .text.HAL_PWR_DisableWakeUpPin:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:240    .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:296    .text.HAL_PWR_DisableWakeUpPin:00000040 $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:302    .text.HAL_PWR_EnterSLEEPMode:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:308    .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:390    .text.HAL_PWR_EnterSLEEPMode:00000048 $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:396    .text.HAL_PWR_EnterSTOPMode:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:402    .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:524    .text.HAL_PWR_EnterSTOPMode:00000088 $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:531    .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:537    .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:584    .text.HAL_PWR_EnterSTANDBYMode:00000028 $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:590    .text.HAL_PWR_EnableSleepOnExit:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:596    .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:630    .text.HAL_PWR_EnableSleepOnExit:0000001c $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:635    .text.HAL_PWR_DisableSleepOnExit:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:641    .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:675    .text.HAL_PWR_DisableSleepOnExit:0000001c $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:680    .text.HAL_PWR_EnableSEVOnPend:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:686    .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:720    .text.HAL_PWR_EnableSEVOnPend:0000001c $d
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:725    .text.HAL_PWR_DisableSEVOnPend:00000000 $t
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:731    .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
C:\Users\zl835\AppData\Local\Temp\ccCqdgMJ.s:765    .text.HAL_PWR_DisableSEVOnPend:0000001c $d

UNDEFINED SYMBOLS
assert_failed