stm32h5xx_hal_pwr_ex.c 28 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32h5xx_hal_pwr_ex.c
  4. * @author MCD Application Team
  5. * @brief Extended PWR HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the Power Controller extension peripheral :
  8. * + Power Supply Control Functions
  9. * + Voltage Monitoring Functions
  10. * + Wakeup Pins configuration Functions
  11. * + Memories Retention Functions
  12. * + IO and JTAG Retention Functions
  13. ******************************************************************************
  14. * @attention
  15. *
  16. * Copyright (c) 2023 STMicroelectronics.
  17. * All rights reserved.
  18. *
  19. * This software is licensed under terms that can be found in the LICENSE file
  20. * in the root directory of this software component.
  21. * If no LICENSE file comes with this software, it is provided AS-IS.
  22. *
  23. ******************************************************************************
  24. */
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32h5xx_hal.h"
  27. /** @addtogroup STM32H5xx_HAL_Driver
  28. * @{
  29. */
  30. /** @defgroup PWREx PWREx
  31. * @brief PWR Extended HAL module driver
  32. * @{
  33. */
  34. #if defined (HAL_PWR_MODULE_ENABLED)
  35. /* Private typedef -----------------------------------------------------------*/
  36. /* Private define ------------------------------------------------------------*/
  37. /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
  38. * @{
  39. */
  40. /* PORTI pins mask */
  41. #define PWR_PORTI_AVAILABLE_PINS (0xFFU)
  42. /*!< Time out value of flags setting */
  43. #define PWR_FLAG_SETTING_DELAY (0x32U)
  44. /** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
  45. * @{
  46. */
  47. #define PVM_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVM trigger */
  48. #define PVM_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVM trigger */
  49. #define PVM_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVM threshold crossing */
  50. #define PVM_MODE_EVT (0x08U) /*!< Mask for event yielded by PVM threshold crossing */
  51. /**
  52. * @}
  53. */
  54. /** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins offsets
  55. * @{
  56. */
  57. /* Wake-Up Pins PWR Pin Pull shift offsets */
  58. #define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
  59. /**
  60. * @}
  61. */
  62. /**
  63. * @}
  64. */
  65. /* Private macro -------------------------------------------------------------*/
  66. /* Private variables ---------------------------------------------------------*/
  67. /* Private function prototypes -----------------------------------------------*/
  68. /* Exported functions --------------------------------------------------------*/
  69. /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
  70. * @{
  71. */
  72. /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
  73. * @brief Power supply control functions
  74. *
  75. @verbatim
  76. ===============================================================================
  77. ##### Power supply control functions #####
  78. ===============================================================================
  79. [..]
  80. @endverbatim
  81. * @{
  82. */
  83. /**
  84. * @brief Configure the system Power Supply.
  85. * @param SupplySource : Specifies the Power Supply source to set after a
  86. * system startup.
  87. * This parameter can be one of the following values :
  88. * @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are
  89. * Bypassed. The Vcore Power
  90. * Domains are supplied from
  91. * external source.
  92. * @retval HAL status.
  93. */
  94. HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
  95. {
  96. uint32_t tickstart;
  97. /* Check the parameters */
  98. assert_param(IS_PWR_SUPPLY(SupplySource));
  99. if ((PWR->SCCR & PWR_SCCR_BYPASS) != (PWR_SCCR_BYPASS))
  100. {
  101. /* Set the power supply configuration */
  102. MODIFY_REG(PWR->SCCR, PWR_SUPPLY_CONFIG_MASK, SupplySource);
  103. /* Get tick */
  104. tickstart = HAL_GetTick();
  105. /* Wait till voltage level flag is set */
  106. while (__HAL_PWR_GET_FLAG(PWR_FLAG_ACTVOSRDY) == 0U)
  107. {
  108. if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
  109. {
  110. return HAL_ERROR;
  111. }
  112. }
  113. }
  114. return HAL_OK;
  115. }
  116. /**
  117. * @brief Get the power supply configuration.
  118. * @retval The supply configuration.
  119. */
  120. uint32_t HAL_PWREx_GetSupplyConfig(void)
  121. {
  122. return (PWR->SCCR & PWR_SUPPLY_CONFIG_MASK);
  123. }
  124. /**
  125. * @brief Configure the main internal regulator output voltage.
  126. * @param VoltageScaling : Specifies the regulator output voltage to achieve
  127. * a tradeoff between performance and power
  128. * consumption.
  129. * This parameter can be one of the following values :
  130. * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
  131. * Scale 0 mode.
  132. * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
  133. * range 1 mode.
  134. * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
  135. * range 2 mode.
  136. * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
  137. * range 3 mode.
  138. * @retval HAL Status
  139. */
  140. HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
  141. {
  142. uint32_t tickstart = HAL_GetTick();
  143. /* Check the parameters */
  144. assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
  145. /* Get the voltage scaling */
  146. if ((PWR->VOSSR & PWR_VOSSR_ACTVOS) == (VoltageScaling << 10U))
  147. {
  148. /* Old and new voltage scaling configuration match : nothing to do */
  149. return HAL_OK;
  150. }
  151. /* Set the voltage range */
  152. MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling);
  153. /* Wait till voltage level flag is set */
  154. while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == 0U)
  155. {
  156. if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
  157. {
  158. return HAL_ERROR;
  159. }
  160. }
  161. return HAL_OK;
  162. }
  163. /**
  164. * @brief Get the main internal regulator output voltage. Reflecting the last
  165. * VOS value applied to the PMU.
  166. * @retval The current applied VOS selection.
  167. */
  168. uint32_t HAL_PWREx_GetVoltageRange(void)
  169. {
  170. /* Get the active voltage scaling */
  171. return (PWR->VOSSR & PWR_VOSSR_ACTVOS);
  172. }
  173. /**
  174. * @brief Configure the main internal regulator output voltage in STOP mode.
  175. * @param VoltageScaling : Specifies the regulator output voltage when the
  176. * system enters Stop mode to achieve a tradeoff between performance
  177. * and power consumption.
  178. * This parameter can be one of the following values:
  179. * @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range
  180. * 3 mode.
  181. * @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range
  182. * 4 mode.
  183. * @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range
  184. * 5 mode.
  185. * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage
  186. * regulator in Low-power (LP) mode to further reduce power consumption.
  187. * When preselecting SVOS3, the use of the voltage regulator low-power
  188. * mode (LP) can be selected by LPDS register bit.
  189. * @note The selected SVOS4 and SVOS5 levels add an additional startup delay
  190. * when exiting from system Stop mode.
  191. * @retval HAL Status.
  192. */
  193. HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling)
  194. {
  195. /* Check the parameters */
  196. assert_param(IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VoltageScaling));
  197. /* Return the stop mode voltage range */
  198. MODIFY_REG(PWR->PMCR, PWR_PMCR_SVOS, VoltageScaling);
  199. return HAL_OK;
  200. }
  201. /**
  202. * @brief Get the main internal regulator output voltage in STOP mode.
  203. * @retval The actual applied VOS selection.
  204. */
  205. uint32_t HAL_PWREx_GetStopModeVoltageRange(void)
  206. {
  207. /* Return the stop voltage scaling */
  208. return (PWR->PMCR & PWR_PMCR_SVOS);
  209. }
  210. /**
  211. * @}
  212. */
  213. /** @defgroup PWREx_Exported_Functions_Group2 Voltage Monitoring Functions
  214. * @brief Voltage monitoring functions
  215. *
  216. @verbatim
  217. ===============================================================================
  218. ##### Voltage Monitoring Functions #####
  219. ===============================================================================
  220. [..]
  221. @endverbatim
  222. * @{
  223. */
  224. /**
  225. * @brief Configure the event mode and the voltage threshold detected by the
  226. * Analog Voltage Detector (AVD).
  227. * @param sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains
  228. * the configuration information for the AVD.
  229. * @note Refer to the electrical characteristics of your device datasheet for
  230. * more details about the voltage threshold corresponding to each
  231. * detection level.
  232. * @retval None.
  233. */
  234. void HAL_PWREx_ConfigAVD(const PWREx_AVDTypeDef *sConfigAVD)
  235. {
  236. /* Check the parameters */
  237. assert_param(IS_PWR_AVD_LEVEL(sConfigAVD->AVDLevel));
  238. assert_param(IS_PWR_AVD_MODE(sConfigAVD->Mode));
  239. /* Set the ALS[10:9] bits according to AVDLevel value */
  240. MODIFY_REG(PWR->VMCR, PWR_VMCR_ALS, sConfigAVD->AVDLevel);
  241. /* Clear any previous config */
  242. __HAL_PWR_AVD_EXTI_DISABLE_EVENT();
  243. __HAL_PWR_AVD_EXTI_DISABLE_IT();
  244. __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();
  245. __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();
  246. /* Configure the interrupt mode */
  247. if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
  248. {
  249. __HAL_PWR_AVD_EXTI_ENABLE_IT();
  250. }
  251. /* Configure the event mode */
  252. if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
  253. {
  254. __HAL_PWR_AVD_EXTI_ENABLE_EVENT();
  255. }
  256. /* Rising edge configuration */
  257. if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
  258. {
  259. __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();
  260. }
  261. /* Falling edge configuration */
  262. if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
  263. {
  264. __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();
  265. }
  266. }
  267. /**
  268. * @brief Enable the Analog Voltage Detector (AVD).
  269. * @retval None.
  270. */
  271. void HAL_PWREx_EnableAVD(void)
  272. {
  273. /* Enable the Analog Voltage Detector */
  274. SET_BIT(PWR->VMCR, PWR_VMCR_AVDEN);
  275. }
  276. /**
  277. * @brief Disable the Analog Voltage Detector(AVD).
  278. * @retval None.
  279. */
  280. void HAL_PWREx_DisableAVD(void)
  281. {
  282. /* Disable the Analog Voltage Detector */
  283. CLEAR_BIT(PWR->VMCR, PWR_VMCR_AVDEN);
  284. }
  285. #if defined (PWR_USBSCR_USB33DEN)
  286. /**
  287. * @brief Enable the USB voltage level detector.
  288. * @retval None.
  289. */
  290. void HAL_PWREx_EnableUSBVoltageDetector(void)
  291. {
  292. /* Enable the USB voltage detector */
  293. SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN);
  294. }
  295. /**
  296. * @brief Disable the USB voltage level detector.
  297. * @retval None.
  298. */
  299. void HAL_PWREx_DisableUSBVoltageDetector(void)
  300. {
  301. /* Disable the USB voltage detector */
  302. CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN);
  303. }
  304. /**
  305. * @brief Enable VDDUSB supply.
  306. * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply
  307. * is present for consumption saving.
  308. * @retval None.
  309. */
  310. void HAL_PWREx_EnableVddUSB(void)
  311. {
  312. SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV);
  313. }
  314. /**
  315. * @brief Disable VDDUSB supply.
  316. * @retval None.
  317. */
  318. void HAL_PWREx_DisableVddUSB(void)
  319. {
  320. CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV);
  321. }
  322. #endif /* PWR_USBSCR_USB33DEN */
  323. /**
  324. * @brief Enable the VBAT and temperature monitoring.
  325. * @retval None.
  326. */
  327. void HAL_PWREx_EnableMonitoring(void)
  328. {
  329. SET_BIT(PWR->BDCR, PWR_BDCR_MONEN);
  330. }
  331. /**
  332. * @brief Disable the VBAT and temperature monitoring.
  333. * @retval None.
  334. */
  335. void HAL_PWREx_DisableMonitoring(void)
  336. {
  337. CLEAR_BIT(PWR->BDCR, PWR_BDCR_MONEN);
  338. }
  339. #if defined (PWR_UCPDR_UCPD_STBY)
  340. /**
  341. * @brief Enable UCPD configuration memorization in Standby mode.
  342. * @retval None.
  343. */
  344. void HAL_PWREx_EnableUCPDStandbyMode(void)
  345. {
  346. SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY);
  347. }
  348. /**
  349. * @brief Disable UCPD configuration memorization in Standby mode.
  350. * @note This function must be called on exiting the Standby mode and before
  351. * any UCPD configuration update.
  352. * @retval None.
  353. */
  354. void HAL_PWREx_DisableUCPDStandbyMode(void)
  355. {
  356. CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY);
  357. }
  358. #endif /* PWR_UCPDR_UCPD_STBY */
  359. #if defined (PWR_UCPDR_UCPD_DBDIS)
  360. /**
  361. * @brief Enable dead battery behavior.
  362. * @note After exiting reset, the USB Type-C (dead battery) behavior is
  363. * enabled, which may have a pull-down effect on CC1 and CC2 pins.
  364. * It is recommended to disable it in all cases, either to stop this
  365. * pull-down or to handover control to the UCPD (the UCPD must be
  366. * initialized before doing the disable).
  367. * @retval None.
  368. */
  369. void HAL_PWREx_EnableUCPDDeadBattery(void)
  370. {
  371. CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
  372. }
  373. /**
  374. * @brief Disable dead battery behavior.
  375. * @note After exiting reset, the USB Type-C (dead battery) behavior is
  376. * enabled, which may have a pull-down effect on CC1 and CC2 pins.
  377. * It is recommended to disable it in all cases, either to stop this
  378. * pull-down or to handover control to the UCPD (the UCPD must be
  379. * initialized before doing the disable).
  380. * @retval None.
  381. */
  382. void HAL_PWREx_DisableUCPDDeadBattery(void)
  383. {
  384. SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS);
  385. }
  386. #endif /* PWR_UCPDR_UCPD_DBDIS */
  387. /**
  388. * @brief Enable the Battery charging.
  389. * @note When VDD is present, charge the external battery through an internal
  390. * resistor.
  391. * @param ResistorValue : Specifies the charging resistor.
  392. * This parameter can be one of the following values :
  393. * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
  394. * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
  395. * @retval None.
  396. */
  397. void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue)
  398. {
  399. /* Check the parameter */
  400. assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue));
  401. /* Specify the charging resistor */
  402. MODIFY_REG(PWR->BDCR, PWR_BDCR_VBRS, ResistorValue);
  403. /* Enable the Battery charging */
  404. SET_BIT(PWR->BDCR, PWR_BDCR_VBE);
  405. }
  406. /**
  407. * @brief Disable the Battery charging.
  408. * @retval None.
  409. */
  410. void HAL_PWREx_DisableBatteryCharging(void)
  411. {
  412. CLEAR_BIT(PWR->BDCR, PWR_BDCR_VBE);
  413. }
  414. /**
  415. * @brief Enable the booster to guarantee the analog switch AC performance when
  416. * the VDD supply voltage is below 2V7.
  417. * @note The VDD supply voltage can be monitored through the PVD and the PLS
  418. * field bits.
  419. * @retval None.
  420. */
  421. void HAL_PWREx_EnableAnalogBooster(void)
  422. {
  423. /* Enable the Analog voltage */
  424. SET_BIT(PWR->PMCR, PWR_PMCR_AVD_READY);
  425. /* Enable VDDA booster */
  426. SET_BIT(PWR->PMCR, PWR_PMCR_BOOSTE);
  427. }
  428. /**
  429. * @brief Disable the analog booster.
  430. * @retval None.
  431. */
  432. void HAL_PWREx_DisableAnalogBooster(void)
  433. {
  434. /* Disable VDDA booster */
  435. CLEAR_BIT(PWR->PMCR, PWR_PMCR_BOOSTE);
  436. /* Disable the Analog voltage */
  437. CLEAR_BIT(PWR->PMCR, PWR_PMCR_AVD_READY);
  438. }
  439. /**
  440. * @brief This function handles the PWR PVD/AVD interrupt request.
  441. * @note This API should be called under the PVD_AVD_IRQHandler().
  442. * @note The use of this API is when the PVD and AVD are activated at the same time.
  443. * @retval None
  444. */
  445. void HAL_PWREx_PVD_AVD_IRQHandler(void)
  446. {
  447. /* Check PWR PVD AVD EXTI Rising flag */
  448. if (__HAL_PWR_PVD_AVD_EXTI_GET_RISING_FLAG() != 0U)
  449. {
  450. /* Clear PWR PVD AVD EXTI Rising pending bit */
  451. WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVD);
  452. /* PWR PVD AVD Rising interrupt user callback */
  453. HAL_PWREx_PVD_AVD_Rising_Callback();
  454. }
  455. /* Check PWR PVD AVD EXTI Falling flag */
  456. if (__HAL_PWR_PVD_AVD_EXTI_GET_FALLING_FLAG() != 0U)
  457. {
  458. /* Clear PWR PVD AVD EXTI Falling pending bit */
  459. WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVD);
  460. /* PWR PVD AVD Falling interrupt user callback */
  461. HAL_PWREx_PVD_AVD_Falling_Callback();
  462. }
  463. }
  464. /**
  465. * @brief PWR PVD AVD Rising interrupt callback.
  466. * @retval None.
  467. */
  468. __weak void HAL_PWREx_PVD_AVD_Rising_Callback(void)
  469. {
  470. /* NOTE : This function should not be modified, when the callback is needed,
  471. the HAL_PWR_AVDCallback can be implemented in the user file
  472. */
  473. }
  474. /**
  475. * @brief PWR PVD AVD Falling interrupt callback.
  476. * @retval None.
  477. */
  478. __weak void HAL_PWREx_PVD_AVD_Falling_Callback(void)
  479. {
  480. /* NOTE : This function should not be modified, when the callback is needed,
  481. the HAL_PWR_AVDCallback can be implemented in the user file
  482. */
  483. }
  484. /**
  485. * @}
  486. */
  487. /** @defgroup PWREx_Exported_Functions_Group3 Wakeup Pins configuration Functions
  488. * @brief Wakeup Pins configuration functions
  489. *
  490. @verbatim
  491. ===============================================================================
  492. ##### Wakeup Pins configuration Functions #####
  493. ===============================================================================
  494. [..]
  495. @endverbatim
  496. * @{
  497. */
  498. /**
  499. * @brief Enable the Wake-up PINx functionality.
  500. * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
  501. * contains the configuration information for the wake-up
  502. * Pin.
  503. * @retval None.
  504. */
  505. void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams)
  506. {
  507. uint32_t pinConfig;
  508. uint32_t regMask;
  509. const uint32_t pullMask = PWR_WUCR_WUPPUPD1;
  510. /* Check the parameters */
  511. assert_param(IS_PWR_WAKEUP_PIN(sPinParams->WakeUpPin));
  512. assert_param(IS_PWR_WAKEUP_PIN_POLARITY(sPinParams->PinPolarity));
  513. assert_param(IS_PWR_WAKEUP_PIN_PULL(sPinParams->PinPull));
  514. pinConfig = sPinParams->WakeUpPin | \
  515. (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WUCR_WUPP1_Pos) & 0x1FU)) | \
  516. (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) \
  517. + PWR_WUCR_WUPPUPD1_Pos) & 0x1FU));
  518. regMask = sPinParams->WakeUpPin | \
  519. (PWR_WUCR_WUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
  520. (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU));
  521. /* Enable and Specify the Wake-Up pin polarity and the pull configuration
  522. for the event detection (rising or falling edge) */
  523. MODIFY_REG(PWR->WUCR, regMask, pinConfig);
  524. }
  525. /**
  526. * @brief Disable the Wake-up PINx functionality.
  527. * @param WakeUpPinx : Specifies the Wake-Up pin to be disabled.
  528. * This parameter can be one of the following values:
  529. * @arg PWR_WAKEUP_PIN1
  530. * @arg PWR_WAKEUP_PIN2
  531. * @arg PWR_WAKEUP_PIN3
  532. * @arg PWR_WAKEUP_PIN4
  533. * @arg PWR_WAKEUP_PIN5
  534. * @arg PWR_WAKEUP_PIN6
  535. * @arg PWR_WAKEUP_PIN7
  536. * @arg PWR_WAKEUP_PIN8
  537. * @note The PWR_WAKEUP_PIN6, PWR_WAKEUP_PIN7 and PWR_WAKEUP_PIN8 are not available for
  538. * STM32H503xx devices.
  539. * @retval None
  540. */
  541. void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPinx)
  542. {
  543. /* Check the parameter */
  544. assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  545. /* Disable the WakeUpPin */
  546. CLEAR_BIT(PWR->WUCR, (PWR_WUCR_WUPEN & WakeUpPinx));
  547. }
  548. /**
  549. * @}
  550. */
  551. /** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions
  552. * @brief Memories retention functions
  553. *
  554. @verbatim
  555. ===============================================================================
  556. ##### Memories Retention Functions #####
  557. ===============================================================================
  558. [..]
  559. @endverbatim
  560. * @{
  561. */
  562. /**
  563. * @brief Enable the Flash Power Down in Stop mode.
  564. * @note When Flash Power Down is enabled the Flash memory enters low-power
  565. * mode. This feature allows to
  566. * obtain the best trade-off between low-power consumption and restart
  567. * time when exiting from Stop mode.
  568. * @retval None.
  569. */
  570. void HAL_PWREx_EnableFlashPowerDown(void)
  571. {
  572. /* Enable the Flash Power Down */
  573. SET_BIT(PWR->PMCR, PWR_PMCR_FLPS);
  574. }
  575. /**
  576. * @brief Disable the Flash Power Down in Stop mode.
  577. * @note When Flash Power Down is disabled the Flash memory is kept on
  578. * normal mode. This feature allows
  579. * to obtain the best trade-off between low-power consumption and
  580. * restart time when exiting from Stop mode.
  581. * @retval None.
  582. */
  583. void HAL_PWREx_DisableFlashPowerDown(void)
  584. {
  585. /* Disable the Flash Power Down */
  586. CLEAR_BIT(PWR->PMCR, PWR_PMCR_FLPS);
  587. }
  588. /**
  589. * @brief Enable memory block shut-off in Stop mode
  590. * @note In Stop mode, the content of the memory blocks is
  591. * maintained. Further power optimization can be obtained by switching
  592. * off some memory blocks. This optimization implies loss of the memory
  593. * content. The user can select which memory is discarded during STOP
  594. * mode by means of xxSO bits.
  595. * @param MemoryBlock : Specifies the memory block to shut-off during Stop mode.
  596. * This parameter can be one of the following values for STM32H573xx/STM32H563xx/STM32H562xx :
  597. * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode
  598. * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode
  599. * @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode
  600. * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode
  601. * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
  602. * This parameter can be one of the following values for STM32H533xx/STM32H523xx :
  603. * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode
  604. * @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control
  605. * in Stop mode
  606. * @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control
  607. * in Stop mode
  608. * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode
  609. * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
  610. * This parameter can be one of the following values for STM32H503xx :
  611. * @arg PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO : RAM2 shut-off control in Stop mode
  612. * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
  613. * @retval None.
  614. */
  615. void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock)
  616. {
  617. /* Check the parameter */
  618. assert_param(IS_PWR_MEMORY_BLOCK(MemoryBlock));
  619. /* Enable memory block shut-off */
  620. SET_BIT(PWR->PMCR, MemoryBlock);
  621. }
  622. /**
  623. * @brief Disable memory block shut-off in Stop mode
  624. * @param MemoryBlock : Specifies the memory block to keep content during
  625. * Stop mode.
  626. * This parameter can be one of the following values for STM32H573xx/STM32H563xx/STM32H562xx :
  627. * @arg PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO : Ethernet shut-off control in Stop mode
  628. * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode
  629. * @arg PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO : RAM2 16k byte shut-off control in Stop mode
  630. * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode
  631. * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
  632. * This parameter can be one of the following values for STM32H533xx/STM32H523xx :
  633. * @arg PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO : RAM3 shut-off control in Stop mode
  634. * @arg PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO : RAM2 Low 16k byte shut-off control
  635. * in Stop mode
  636. * @arg PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO : RAM2 High 16k byte shut-off control
  637. * in Stop mode
  638. * @arg PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO : RAM2 48k byte shut-off control in Stop mode
  639. * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
  640. * This parameter can be one of the following values for STM32H503xx :
  641. * @arg PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO : RAM2 shut-off control in Stop mode
  642. * @arg PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO : RAM1 shut-off control in Stop mode
  643. * @retval None.
  644. */
  645. void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock)
  646. {
  647. /* Check the parameter */
  648. assert_param(IS_PWR_MEMORY_BLOCK(MemoryBlock));
  649. /* Disable memory block shut-off */
  650. CLEAR_BIT(PWR->PMCR, MemoryBlock);
  651. }
  652. /**
  653. * @brief Enable the Backup RAM retention in Standby and VBAT modes.
  654. * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and
  655. * Stop modes. However, its content is lost in Standby, Shutdown and
  656. * VBAT modes. This bit can be writte
  657. * @retval None.
  658. */
  659. HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void)
  660. {
  661. SET_BIT(PWR->BDCR, PWR_BDCR_BREN);
  662. return HAL_OK;
  663. }
  664. /**
  665. * @brief Disable the Backup RAM retention in Standby and VBAT modes.
  666. * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and
  667. * Stop modes. However, its content is lost in Standby, Shutdown and
  668. * VBAT modes. This bit can be write
  669. * @retval None.
  670. */
  671. void HAL_PWREx_DisableBkupRAMRetention(void)
  672. {
  673. CLEAR_BIT(PWR->BDCR, PWR_BDCR_BREN);
  674. }
  675. /**
  676. * @}
  677. */
  678. /** @defgroup PWREx_Exported_Functions_Group5 IO and JTAG Retention Functions
  679. * @brief IO and JTAG Retention functions
  680. *
  681. @verbatim
  682. ===============================================================================
  683. ##### IO and JTAG Retention Functions #####
  684. ===============================================================================
  685. [..]
  686. In the Standby mode, the I/Os are by default in floating state. If the IORETEN bit in the
  687. PWR_IORETR register is set, the I/Os output state is retained. IO Retention mode is
  688. enabled for all IO except the IO support the standby functionality and JTAG IOs (PA13,
  689. PA14, PA15 and PB4). When entering into Standby mode, the state of the output is
  690. sampled, and pull-up or pull-down resistor are set to maintain the IO output during Standby
  691. mode.
  692. If the JTAGIORETEN bit in the PWR_IORETR register is set, the I/Os output state is
  693. retained. IO Retention mode is enabled for PA13, PA14, PA15 and PB4 (default JTAG pullup/
  694. pull-down after wakeup are not enabled).
  695. @endverbatim
  696. * @{
  697. */
  698. /**
  699. * @brief Enable GPIO state retention in Standby mode.
  700. * @note When entering into standby mode, the output is sampled, and applied to the output IO during
  701. * the standby power mode
  702. * @retval None.
  703. */
  704. void HAL_PWREx_EnableStandbyIORetention(void)
  705. {
  706. /* Enable GPIO state retention */
  707. SET_BIT(PWR->IORETR, PWR_IORETR_IORETEN);
  708. }
  709. /**
  710. * @brief Disable GPIO state retention in Standby mode.
  711. * @retval None.
  712. */
  713. void HAL_PWREx_DisableStandbyIORetention(void)
  714. {
  715. /* Disable GPIO state retention */
  716. CLEAR_BIT(PWR->IORETR, PWR_IORETR_IORETEN);
  717. }
  718. /**
  719. * @brief Enable JTAG IOs state retention in Standby mode.
  720. * @note when entering into standby mode, the output is sampled, and applied to the output IO during
  721. * the standby power mode
  722. * @retval None.
  723. */
  724. void HAL_PWREx_EnableStandbyJTAGIORetention(void)
  725. {
  726. /* Enable JTAG IOs state retention */
  727. SET_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN);
  728. }
  729. /**
  730. * @brief Disable JTAG IOs state retention in Standby mode.
  731. * @retval None.
  732. */
  733. void HAL_PWREx_DisableStandbyJTAGIORetention(void)
  734. {
  735. /* Enable JTAG IOs state retention */
  736. CLEAR_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN);
  737. }
  738. /**
  739. * @}
  740. */
  741. #endif /* defined (HAL_PWR_MODULE_ENABLED) */
  742. /**
  743. * @}
  744. */
  745. /**
  746. * @}
  747. */
  748. /**
  749. * @}
  750. */