stm32h5xx_hal_dma.c 56 KB

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  1. /**
  2. **********************************************************************************************************************
  3. * @file stm32h5xx_hal_dma.c
  4. * @author MCD Application Team
  5. * @brief This file provides firmware functions to manage the following functionalities of the Direct Memory Access
  6. * (DMA) peripheral:
  7. * + Initialization/De-Initialization Functions
  8. * + I/O Operation Functions
  9. * + State and Errors Functions
  10. * + DMA Attributes Functions
  11. *
  12. **********************************************************************************************************************
  13. * @attention
  14. *
  15. * Copyright (c) 2023 STMicroelectronics.
  16. * All rights reserved.
  17. *
  18. * This software is licensed under terms that can be found in the LICENSE file
  19. * in the root directory of this software component.
  20. * If no LICENSE file comes with this software, it is provided AS-IS.
  21. *
  22. **********************************************************************************************************************
  23. @verbatim
  24. ======================================================================================================================
  25. ##### How to use this driver #####
  26. ======================================================================================================================
  27. [..]
  28. DMA transfer modes are divided to 2 major categories :
  29. (+) Normal transfers (legacy)
  30. (+) Linked-list transfers
  31. [..]
  32. Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended
  33. module.
  34. [..]
  35. Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended
  36. module as extensions to normal mode.
  37. Advanced features are :
  38. (+) Repeated block feature.
  39. (+) Trigger feature.
  40. (+) Data handling feature.
  41. [..]
  42. DMA Legacy circular transfer, is replaced by circular linked-list configuration.
  43. *** Initialization and De-Initialization ***
  44. ============================================
  45. [..]
  46. For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal
  47. SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between
  48. peripherals and DMA requests.
  49. [..]
  50. For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through
  51. the following parameters:
  52. (+) Request : Specifies the DMA channel request
  53. Request parameters :
  54. (++) can be a value of DMA_Request_Selection
  55. (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel
  56. (++) can be a value of DMA_Block_Request
  57. (+) Direction : Specifies the transfer direction for DMA channel
  58. (++) can be a value of DMA_Transfer_Direction
  59. (+) SrcInc : Specifies the source increment mode for the DMA channel
  60. (++) can be a value of DMA_Source_Increment_Mode
  61. (+) DestInc : Specifies the destination increment mode for the DMA channel
  62. (++) can be a value of DMA_Destination_Increment_Mode
  63. (+) SrcDataWidth : Specifies the source data width for the DMA channel
  64. (++) can be a value of DMA_Source_Data_Width
  65. (+) DestDataWidth : Specifies the destination data width for the DMA channel
  66. (++) can be a value of DMA_Destination_Data_Width
  67. (+) Priority : Specifies the priority for the DMA channel
  68. (++) can be a value of DMA_Priority_Level
  69. (+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel
  70. (++) can be a value of between 1 and 64
  71. (+) DestBurstLength : Specifies the destination burst length (number of beats) for the DMA channel
  72. (++) can be a value of between 1 and 64
  73. (+) TransferAllocatedPort : Specifies the source and destination allocated ports
  74. (++) can be a value of DMA_Transfer_Allocated_Port
  75. (+) TransferEventMode : Specifies the transfer event mode for the DMA channel
  76. (++) can be a value of DMA_Transfer_Event_Mode
  77. (+) Mode : Specifies the transfer mode for the DMA channel
  78. (++) can be one of the following modes :
  79. (+++) DMA_NORMAL : Normal Mode
  80. (+++) DMA_PFCTRL : Peripheral Flow Control (peripheral early termination) Mode
  81. *** Polling mode IO operation ***
  82. =================================
  83. [..]
  84. (+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination
  85. address and the size of data to be transferred.
  86. (+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be
  87. configured by User depending on his application.
  88. Transfer level can be :
  89. (++) HAL_DMA_HALF_TRANSFER
  90. (++) HAL_DMA_FULL_TRANSFER
  91. For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code.
  92. (+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode.
  93. This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA
  94. channel. (This API should not be called from an interrupt service routine)
  95. *** Interrupt mode IO operation ***
  96. ===================================
  97. [..]
  98. (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
  99. (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
  100. (+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list :
  101. (++) XferCpltCallback : transfer complete callback.
  102. (++) XferHalfCpltCallback : half transfer complete callback.
  103. (++) XferErrorCallback : transfer error callback.
  104. (++) XferAbortCallback : transfer abort complete callback.
  105. (++) XferSuspendCallback : transfer suspend complete callback.
  106. (+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration
  107. of source address,destination address and the size of data to be transferred.
  108. (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt.
  109. (+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode.
  110. This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended,
  111. an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback
  112. XferAbortCallback. (This API could be called from an interrupt service routine)
  113. *** State and errors ***
  114. ========================
  115. [..]
  116. (+) Use HAL_DMA_GetState() function to get the DMA state.
  117. (+) Use HAL_DMA_GetError() function to get the DMA error code.
  118. *** Security and privilege attributes ***
  119. =========================================
  120. [..]
  121. (+) Use HAL_DMA_ConfigChannelAttributes() function to configure DMA channel security and privilege attributes.
  122. (++) Security : at channel level, at source level and at destination level.
  123. (++) Privilege : at channel level.
  124. (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes.
  125. (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes
  126. configuration. This API can be called once after each system boot.
  127. If called again, HAL_DMA_ConfigChannelAttributes() API has no effect.
  128. Unlock is done either by a system boot or a by an RCC reset.
  129. (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status.
  130. *** DMA HAL driver macros list ***
  131. ==================================
  132. [..]
  133. Below the list of most used macros in DMA HAL driver.
  134. (+) __HAL_DMA_ENABLE : Enable the specified DMA Channel.
  135. (+) __HAL_DMA_DISABLE : Disable the specified DMA Channel.
  136. (+) __HAL_DMA_GET_FLAG : Get the DMA Channel pending flags.
  137. (+) __HAL_DMA_CLEAR_FLAG : Clear the DMA Channel pending flags.
  138. (+) __HAL_DMA_ENABLE_IT : Enable the specified DMA Channel interrupts.
  139. (+) __HAL_DMA_DISABLE_IT : Disable the specified DMA Channel interrupts.
  140. (+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not.
  141. [..]
  142. (@) You can refer to the header file of the DMA HAL driver for more useful macros.
  143. @endverbatim
  144. **********************************************************************************************************************
  145. */
  146. /* Includes ----------------------------------------------------------------------------------------------------------*/
  147. #include "stm32h5xx_hal.h"
  148. /** @addtogroup STM32H5xx_HAL_Driver
  149. * @{
  150. */
  151. /** @defgroup DMA DMA
  152. * @brief DMA HAL module driver
  153. * @{
  154. */
  155. #ifdef HAL_DMA_MODULE_ENABLED
  156. /* Private typedef ---------------------------------------------------------------------------------------------------*/
  157. /* Private constants -------------------------------------------------------------------------------------------------*/
  158. /* Private macro -----------------------------------------------------------------------------------------------------*/
  159. /* Private variables -------------------------------------------------------------------------------------------------*/
  160. /* Private function prototypes ---------------------------------------------------------------------------------------*/
  161. static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma,
  162. uint32_t SrcAddress,
  163. uint32_t DstAddress,
  164. uint32_t SrcDataSize);
  165. static void DMA_Init(DMA_HandleTypeDef const *const hdma);
  166. /* Exported functions ------------------------------------------------------------------------------------------------*/
  167. /** @addtogroup DMA_Exported_Functions DMA Exported Functions
  168. * @{
  169. */
  170. /** @addtogroup DMA_Exported_Functions_Group1
  171. *
  172. @verbatim
  173. ======================================================================================================================
  174. ##### Initialization and de-initialization functions #####
  175. ======================================================================================================================
  176. [..]
  177. This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode.
  178. [..]
  179. (+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual.
  180. (+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel.
  181. @endverbatim
  182. * @{
  183. */
  184. /**
  185. * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and
  186. * create the associated handle.
  187. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  188. * specified DMA Channel.
  189. * @retval HAL status.
  190. */
  191. HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma)
  192. {
  193. /* Get tick number */
  194. uint32_t tickstart = HAL_GetTick();
  195. /* Check the DMA peripheral handle parameter */
  196. if (hdma == NULL)
  197. {
  198. return HAL_ERROR;
  199. }
  200. /* Check the parameters */
  201. assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
  202. assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
  203. if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
  204. {
  205. assert_param(IS_DMA_REQUEST(hdma->Init.Request));
  206. }
  207. assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest));
  208. assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc));
  209. assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc));
  210. assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth));
  211. assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth));
  212. assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
  213. assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode));
  214. assert_param(IS_DMA_MODE(hdma->Init.Mode));
  215. if (hdma->Init.Mode == DMA_PFCTRL)
  216. {
  217. assert_param(IS_DMA_PFREQ_INSTANCE(hdma->Instance));
  218. }
  219. /* Check DMA channel instance */
  220. if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
  221. {
  222. assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength));
  223. assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength));
  224. assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort));
  225. }
  226. /* Allocate lock resource */
  227. __HAL_UNLOCK(hdma);
  228. /* Initialize the callbacks */
  229. if (hdma->State == HAL_DMA_STATE_RESET)
  230. {
  231. /* Clean all callbacks */
  232. hdma->XferCpltCallback = NULL;
  233. hdma->XferHalfCpltCallback = NULL;
  234. hdma->XferErrorCallback = NULL;
  235. hdma->XferAbortCallback = NULL;
  236. hdma->XferSuspendCallback = NULL;
  237. }
  238. /* Update the DMA channel state */
  239. hdma->State = HAL_DMA_STATE_BUSY;
  240. /* Disable the DMA channel */
  241. __HAL_DMA_DISABLE(hdma);
  242. /* Check if the DMA channel is effectively disabled */
  243. while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
  244. {
  245. /* Check for the Timeout */
  246. if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
  247. {
  248. /* Update the DMA channel error code */
  249. hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
  250. /* Update the DMA channel state */
  251. hdma->State = HAL_DMA_STATE_ERROR;
  252. return HAL_ERROR;
  253. }
  254. }
  255. /* Initialize the DMA channel registers */
  256. DMA_Init(hdma);
  257. /* Update DMA channel operation mode */
  258. hdma->Mode = hdma->Init.Mode;
  259. /* Update the DMA channel error code */
  260. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  261. /* Update the DMA channel state */
  262. hdma->State = HAL_DMA_STATE_READY;
  263. return HAL_OK;
  264. }
  265. /**
  266. * @brief DeInitialize the DMA channel when it is configured in normal mode.
  267. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  268. * specified DMA Channel.
  269. * @retval HAL status.
  270. */
  271. HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma)
  272. {
  273. DMA_TypeDef *p_dma_instance;
  274. uint32_t tickstart = HAL_GetTick();
  275. /* Check the DMA peripheral handle parameter */
  276. if (hdma == NULL)
  277. {
  278. return HAL_ERROR;
  279. }
  280. /* Check the parameters */
  281. assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
  282. /* Get DMA instance */
  283. p_dma_instance = GET_DMA_INSTANCE(hdma);
  284. /* Disable the selected DMA Channel */
  285. __HAL_DMA_DISABLE(hdma);
  286. /* Check if the DMA channel is effectively disabled */
  287. while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U)
  288. {
  289. /* Check for the Timeout */
  290. if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
  291. {
  292. /* Update the DMA channel error code */
  293. hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
  294. /* Update the DMA channel state */
  295. hdma->State = HAL_DMA_STATE_ERROR;
  296. return HAL_ERROR;
  297. }
  298. }
  299. /* Reset DMA Channel registers */
  300. hdma->Instance->CLBAR = 0U;
  301. hdma->Instance->CCR = 0U;
  302. hdma->Instance->CTR1 = 0U;
  303. hdma->Instance->CTR2 = 0U;
  304. hdma->Instance->CBR1 = 0U;
  305. hdma->Instance->CSAR = 0U;
  306. hdma->Instance->CDAR = 0U;
  307. hdma->Instance->CLLR = 0U;
  308. /* Reset 2D Addressing registers */
  309. if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
  310. {
  311. hdma->Instance->CTR3 = 0U;
  312. hdma->Instance->CBR2 = 0U;
  313. }
  314. /* Clear privilege attribute */
  315. CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
  316. #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
  317. /* Clear secure attribute */
  318. CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU)));
  319. #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
  320. /* Clear all flags */
  321. __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
  322. DMA_FLAG_TO));
  323. /* Clean all callbacks */
  324. hdma->XferCpltCallback = NULL;
  325. hdma->XferHalfCpltCallback = NULL;
  326. hdma->XferErrorCallback = NULL;
  327. hdma->XferAbortCallback = NULL;
  328. hdma->XferSuspendCallback = NULL;
  329. /* Clean DMA queue */
  330. hdma->LinkedListQueue = NULL;
  331. /* Clean DMA parent */
  332. if (hdma->Parent != NULL)
  333. {
  334. hdma->Parent = NULL;
  335. }
  336. /* Update DMA channel operation mode */
  337. hdma->Mode = DMA_NORMAL;
  338. /* Update the DMA channel error code */
  339. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  340. /* Update the DMA channel state */
  341. hdma->State = HAL_DMA_STATE_RESET;
  342. /* Release Lock */
  343. __HAL_UNLOCK(hdma);
  344. return HAL_OK;
  345. }
  346. /**
  347. * @}
  348. */
  349. /** @addtogroup DMA_Exported_Functions_Group2
  350. *
  351. @verbatim
  352. ======================================================================================================================
  353. ##### IO operation functions #####
  354. ======================================================================================================================
  355. [..]
  356. This section provides functions allowing to :
  357. (+) Configure the source, destination address and data size and Start DMA transfer in normal mode
  358. (+) Abort DMA transfer
  359. (+) Poll for transfer complete
  360. (+) Handle DMA interrupt request
  361. (+) Register and Unregister DMA callbacks
  362. [..]
  363. (+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode).
  364. (+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode).
  365. (+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode).
  366. (+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode).
  367. (+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode).
  368. This API cannot be used for circular transfers.
  369. (+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode).
  370. (+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and
  371. unregister user customized callbacks.
  372. User callbacks are called under HAL_DMA_IRQHandler().
  373. @endverbatim
  374. * @{
  375. */
  376. /**
  377. * @brief Start the DMA channel transfer in normal mode (Blocking mode).
  378. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
  379. * the specified DMA Channel.
  380. * @param SrcAddress : The source data address.
  381. * @param DstAddress : The destination data address.
  382. * @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
  383. * @retval HAL status.
  384. */
  385. HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma,
  386. uint32_t SrcAddress,
  387. uint32_t DstAddress,
  388. uint32_t SrcDataSize)
  389. {
  390. /* Check the DMA peripheral handle parameter */
  391. if (hdma == NULL)
  392. {
  393. return HAL_ERROR;
  394. }
  395. /* Check the DMA Mode is DMA_NORMAL */
  396. if (hdma->Mode != DMA_NORMAL)
  397. {
  398. return HAL_ERROR;
  399. }
  400. /* Check the parameters */
  401. assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize));
  402. /* Process locked */
  403. __HAL_LOCK(hdma);
  404. /* Check DMA channel state */
  405. if (hdma->State == HAL_DMA_STATE_READY)
  406. {
  407. /* Update the DMA channel state */
  408. hdma->State = HAL_DMA_STATE_BUSY;
  409. /* Update the DMA channel error code */
  410. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  411. /* Configure the source address, destination address, the data size and clear flags */
  412. DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize);
  413. /* Enable DMA channel */
  414. __HAL_DMA_ENABLE(hdma);
  415. }
  416. else
  417. {
  418. /* Update the DMA channel error code */
  419. hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
  420. /* Process unlocked */
  421. __HAL_UNLOCK(hdma);
  422. return HAL_ERROR;
  423. }
  424. return HAL_OK;
  425. }
  426. /**
  427. * @brief Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode).
  428. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  429. * specified DMA Channel.
  430. * @param SrcAddress : The source data address.
  431. * @param DstAddress : The destination data address.
  432. * @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
  433. * @retval HAL status.
  434. */
  435. HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma,
  436. uint32_t SrcAddress,
  437. uint32_t DstAddress,
  438. uint32_t SrcDataSize)
  439. {
  440. /* Check the DMA peripheral handle parameter */
  441. if (hdma == NULL)
  442. {
  443. return HAL_ERROR;
  444. }
  445. /* Check the DMA Mode is DMA_NORMAL */
  446. if (hdma->Mode != DMA_NORMAL)
  447. {
  448. return HAL_ERROR;
  449. }
  450. /* Check the parameters */
  451. assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize));
  452. /* Process locked */
  453. __HAL_LOCK(hdma);
  454. /* Check DMA channel state */
  455. if (hdma->State == HAL_DMA_STATE_READY)
  456. {
  457. /* Update the DMA channel state */
  458. hdma->State = HAL_DMA_STATE_BUSY;
  459. /* Update the DMA channel error code */
  460. hdma->ErrorCode = HAL_DMA_ERROR_NONE;
  461. /* Configure the source address, destination address, the data size and clear flags */
  462. DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize);
  463. /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */
  464. __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO));
  465. /* Check half transfer complete callback */
  466. if (hdma->XferHalfCpltCallback != NULL)
  467. {
  468. /* If Half Transfer complete callback is set, enable the corresponding IT */
  469. __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
  470. }
  471. /* Check Half suspend callback */
  472. if (hdma->XferSuspendCallback != NULL)
  473. {
  474. /* If Transfer suspend callback is set, enable the corresponding IT */
  475. __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP);
  476. }
  477. /* Enable DMA channel */
  478. __HAL_DMA_ENABLE(hdma);
  479. }
  480. else
  481. {
  482. /* Update the DMA channel error code */
  483. hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
  484. /* Process unlocked */
  485. __HAL_UNLOCK(hdma);
  486. return HAL_ERROR;
  487. }
  488. return HAL_OK;
  489. }
  490. /**
  491. * @brief Abort any on-going DMA channel transfer (Blocking mode).
  492. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  493. * specified DMA Channel.
  494. * @note After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel
  495. * is suspended while a data transfer is on-going, the current data will be transferred and the channel will be
  496. * effectively suspended only after the transfer of any on-going data is finished.
  497. * @retval HAL status.
  498. */
  499. HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma)
  500. {
  501. /* Get tick number */
  502. uint32_t tickstart = HAL_GetTick();
  503. /* Check the DMA peripheral handle parameter */
  504. if (hdma == NULL)
  505. {
  506. return HAL_ERROR;
  507. }
  508. /* Check DMA channel state */
  509. if (hdma->State != HAL_DMA_STATE_BUSY)
  510. {
  511. /* Update the DMA channel error code */
  512. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  513. /* Process Unlocked */
  514. __HAL_UNLOCK(hdma);
  515. return HAL_ERROR;
  516. }
  517. else
  518. {
  519. /* Suspend the channel */
  520. hdma->Instance->CCR |= DMA_CCR_SUSP;
  521. /* Update the DMA channel state */
  522. hdma->State = HAL_DMA_STATE_SUSPEND;
  523. /* Check if the DMA Channel is suspended */
  524. while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U)
  525. {
  526. /* Check for the Timeout */
  527. if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
  528. {
  529. /* Update the DMA channel error code */
  530. hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
  531. /* Update the DMA channel state */
  532. hdma->State = HAL_DMA_STATE_ERROR;
  533. /* Check DMA channel transfer mode */
  534. if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
  535. {
  536. /* Update the linked-list queue state */
  537. hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
  538. }
  539. /* Process Unlocked */
  540. __HAL_UNLOCK(hdma);
  541. return HAL_ERROR;
  542. }
  543. }
  544. /* Reset the channel */
  545. hdma->Instance->CCR |= DMA_CCR_RESET;
  546. /* Update the DMA channel state */
  547. hdma->State = HAL_DMA_STATE_ABORT;
  548. /* Clear all status flags */
  549. __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
  550. DMA_FLAG_TO));
  551. /* Update the DMA channel state */
  552. hdma->State = HAL_DMA_STATE_READY;
  553. /* Check DMA channel transfer mode */
  554. if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
  555. {
  556. /* Update the linked-list queue state */
  557. hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
  558. /* Clear remaining data size to ensure loading linked-list from memory next start */
  559. hdma->Instance->CBR1 = 0U;
  560. }
  561. /* Process Unlocked */
  562. __HAL_UNLOCK(hdma);
  563. }
  564. return HAL_OK;
  565. }
  566. /**
  567. * @brief Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode).
  568. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  569. * specified DMA Channel.
  570. * @retval HAL status.
  571. */
  572. HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma)
  573. {
  574. /* Check the DMA peripheral handle parameter */
  575. if (hdma == NULL)
  576. {
  577. return HAL_ERROR;
  578. }
  579. /* Check DMA channel state */
  580. if (hdma->State != HAL_DMA_STATE_BUSY)
  581. {
  582. /* Update the DMA channel error code */
  583. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  584. return HAL_ERROR;
  585. }
  586. else
  587. {
  588. /* Update the DMA channel state */
  589. hdma->State = HAL_DMA_STATE_ABORT;
  590. /* Suspend the channel and activate suspend interrupt */
  591. hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE);
  592. }
  593. return HAL_OK;
  594. }
  595. /**
  596. * @brief Polling for transfer status (Blocking mode).
  597. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  598. * specified DMA Channel.
  599. * @param CompleteLevel : Specifies the DMA level complete.
  600. * @param Timeout : Timeout duration.
  601. * @retval HAL status
  602. */
  603. HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma,
  604. HAL_DMA_LevelCompleteTypeDef CompleteLevel,
  605. uint32_t Timeout)
  606. {
  607. /* Get tick number */
  608. uint32_t tickstart = HAL_GetTick();
  609. uint32_t level_flag;
  610. uint32_t tmp_csr;
  611. /* Check the DMA peripheral handle parameter */
  612. if (hdma == NULL)
  613. {
  614. return HAL_ERROR;
  615. }
  616. /* Check the parameters */
  617. assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel));
  618. /* Check DMA channel state */
  619. if (hdma->State != HAL_DMA_STATE_BUSY)
  620. {
  621. /* Update the DMA channel error code */
  622. hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
  623. /* Process Unlocked */
  624. __HAL_UNLOCK(hdma);
  625. return HAL_ERROR;
  626. }
  627. /* Polling mode is not supported in circular mode */
  628. if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR)
  629. {
  630. /* Update the DMA channel error code */
  631. hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
  632. return HAL_ERROR;
  633. }
  634. /* Get the level transfer complete flag */
  635. level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT);
  636. /* Get DMA channel status */
  637. tmp_csr = hdma->Instance->CSR;
  638. while ((tmp_csr & level_flag) == 0U)
  639. {
  640. /* Check for the timeout */
  641. if (Timeout != HAL_MAX_DELAY)
  642. {
  643. if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
  644. {
  645. /* Update the DMA channel error code */
  646. hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
  647. /*
  648. If timeout, abort the current transfer.
  649. Note that the Abort function will
  650. - Clear all transfer flags.
  651. - Unlock.
  652. - Set the State.
  653. */
  654. (void)HAL_DMA_Abort(hdma);
  655. return HAL_ERROR;
  656. }
  657. }
  658. /* Get a newer CSR register value */
  659. tmp_csr = hdma->Instance->CSR;
  660. }
  661. /* Check trigger overrun flag */
  662. if ((tmp_csr & DMA_FLAG_TO) != 0U)
  663. {
  664. /* Update the DMA channel error code */
  665. hdma->ErrorCode |= HAL_DMA_ERROR_TO;
  666. /* Clear the error flag */
  667. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO);
  668. }
  669. /* Check error flags */
  670. if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U)
  671. {
  672. /* Check the data transfer error flag */
  673. if ((tmp_csr & DMA_FLAG_DTE) != 0U)
  674. {
  675. /* Update the DMA channel error code */
  676. hdma->ErrorCode |= HAL_DMA_ERROR_DTE;
  677. /* Clear the error flag */
  678. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE);
  679. }
  680. /* Check the update link error flag */
  681. if ((tmp_csr & DMA_FLAG_ULE) != 0U)
  682. {
  683. /* Update the DMA channel error code */
  684. hdma->ErrorCode |= HAL_DMA_ERROR_ULE;
  685. /* Clear the error flag */
  686. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE);
  687. }
  688. /* Check the user setting error flag */
  689. if ((tmp_csr & DMA_FLAG_USE) != 0U)
  690. {
  691. /* Update the DMA channel error code */
  692. hdma->ErrorCode |= HAL_DMA_ERROR_USE;
  693. /* Clear the error flag */
  694. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE);
  695. }
  696. /* Reset the channel */
  697. hdma->Instance->CCR |= DMA_CCR_RESET;
  698. /* Update the DMA channel state */
  699. hdma->State = HAL_DMA_STATE_READY;
  700. /* Check DMA channel transfer mode */
  701. if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
  702. {
  703. /* Update the linked-list queue state */
  704. hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
  705. }
  706. /* Process Unlocked */
  707. __HAL_UNLOCK(hdma);
  708. return HAL_ERROR;
  709. }
  710. /* Clear the transfer level flag */
  711. if (CompleteLevel == HAL_DMA_HALF_TRANSFER)
  712. {
  713. /* Clear the Half Transfer flag */
  714. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT);
  715. }
  716. else if (CompleteLevel == HAL_DMA_FULL_TRANSFER)
  717. {
  718. /* Clear the transfer flags */
  719. __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT));
  720. /* Update the DMA channel state */
  721. hdma->State = HAL_DMA_STATE_READY;
  722. /* Check DMA channel transfer mode */
  723. if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
  724. {
  725. /* Update the linked-list queue state */
  726. hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
  727. }
  728. /* Process unlocked */
  729. __HAL_UNLOCK(hdma);
  730. }
  731. else
  732. {
  733. return HAL_ERROR;
  734. }
  735. return HAL_OK;
  736. }
  737. /**
  738. * @brief Handle DMA interrupt request (Non-blocking mode).
  739. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  740. * specified DMA Channel.
  741. * @retval None.
  742. */
  743. void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma)
  744. {
  745. const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma);
  746. uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
  747. uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag);
  748. #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
  749. uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag);
  750. #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
  751. /* Global Interrupt Flag management *********************************************************************************/
  752. #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
  753. if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U))
  754. #else
  755. if (global_active_flag_ns == 0U)
  756. #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
  757. {
  758. return; /* the global interrupt flag for the current channel is down , nothing to do */
  759. }
  760. /* Data Transfer Error Interrupt management *************************************************************************/
  761. if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U)
  762. {
  763. /* Check if interrupt source is enabled */
  764. if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U)
  765. {
  766. /* Clear the transfer error flag */
  767. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE);
  768. /* Update the DMA channel error code */
  769. hdma->ErrorCode |= HAL_DMA_ERROR_DTE;
  770. }
  771. }
  772. /* Update Linked-list Error Interrupt management ********************************************************************/
  773. if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U)
  774. {
  775. /* Check if interrupt source is enabled */
  776. if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U)
  777. {
  778. /* Clear the update linked-list error flag */
  779. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE);
  780. /* Update the DMA channel error code */
  781. hdma->ErrorCode |= HAL_DMA_ERROR_ULE;
  782. }
  783. }
  784. /* User Setting Error Interrupt management **************************************************************************/
  785. if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U)
  786. {
  787. /* Check if interrupt source is enabled */
  788. if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U)
  789. {
  790. /* Clear the user setting error flag */
  791. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE);
  792. /* Update the DMA channel error code */
  793. hdma->ErrorCode |= HAL_DMA_ERROR_USE;
  794. }
  795. }
  796. /* Trigger Overrun Interrupt management *****************************************************************************/
  797. if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U)
  798. {
  799. /* Check if interrupt source is enabled */
  800. if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U)
  801. {
  802. /* Clear the trigger overrun flag */
  803. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO);
  804. /* Update the DMA channel error code */
  805. hdma->ErrorCode |= HAL_DMA_ERROR_TO;
  806. }
  807. }
  808. /* Half Transfer Complete Interrupt management **********************************************************************/
  809. if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U)
  810. {
  811. /* Check if interrupt source is enabled */
  812. if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
  813. {
  814. /* Clear the half transfer flag */
  815. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT);
  816. /* Check half transfer complete callback */
  817. if (hdma->XferHalfCpltCallback != NULL)
  818. {
  819. /* Half transfer callback */
  820. hdma->XferHalfCpltCallback(hdma);
  821. }
  822. }
  823. }
  824. /* Suspend Transfer Interrupt management ****************************************************************************/
  825. if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U)
  826. {
  827. /* Check if interrupt source is enabled */
  828. if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U)
  829. {
  830. /* Clear the block transfer complete flag */
  831. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP);
  832. /* Check DMA channel state */
  833. if (hdma->State == HAL_DMA_STATE_ABORT)
  834. {
  835. /* Disable the suspend transfer interrupt */
  836. __HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP);
  837. /* Reset the channel internal state and reset the FIFO */
  838. hdma->Instance->CCR |= DMA_CCR_RESET;
  839. /* Update the DMA channel state */
  840. hdma->State = HAL_DMA_STATE_READY;
  841. /* Check DMA channel transfer mode */
  842. if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
  843. {
  844. /* Update the linked-list queue state */
  845. hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
  846. /* Clear remaining data size to ensure loading linked-list from memory next start */
  847. hdma->Instance->CBR1 = 0U;
  848. }
  849. /* Process Unlocked */
  850. __HAL_UNLOCK(hdma);
  851. /* Check transfer abort callback */
  852. if (hdma->XferAbortCallback != NULL)
  853. {
  854. /* Transfer abort callback */
  855. hdma->XferAbortCallback(hdma);
  856. }
  857. return;
  858. }
  859. else
  860. {
  861. /* Update the DMA channel state */
  862. hdma->State = HAL_DMA_STATE_SUSPEND;
  863. /* Check transfer suspend callback */
  864. if (hdma->XferSuspendCallback != NULL)
  865. {
  866. /* Transfer suspend callback */
  867. hdma->XferSuspendCallback(hdma);
  868. }
  869. }
  870. }
  871. }
  872. /* Transfer Complete Interrupt management ***************************************************************************/
  873. if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U)
  874. {
  875. /* Check if interrupt source is enabled */
  876. if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
  877. {
  878. /* Check DMA channel transfer mode */
  879. if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
  880. {
  881. /* If linked-list transfer */
  882. if (hdma->Instance->CLLR == 0U)
  883. {
  884. if (hdma->Instance->CBR1 == 0U)
  885. {
  886. /* Update the DMA channel state */
  887. hdma->State = HAL_DMA_STATE_READY;
  888. /* Update the linked-list queue state */
  889. hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
  890. }
  891. }
  892. }
  893. else
  894. {
  895. /* If normal transfer */
  896. if (hdma->Instance->CBR1 == 0U)
  897. {
  898. /* Update the DMA channel state */
  899. hdma->State = HAL_DMA_STATE_READY;
  900. }
  901. }
  902. /* Clear TC and HT transfer flags */
  903. __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT));
  904. /* Process Unlocked */
  905. __HAL_UNLOCK(hdma);
  906. /* Check transfer complete callback */
  907. if (hdma->XferCpltCallback != NULL)
  908. {
  909. /* Channel Transfer Complete callback */
  910. hdma->XferCpltCallback(hdma);
  911. }
  912. }
  913. }
  914. /* Manage error case ************************************************************************************************/
  915. if (hdma->ErrorCode != HAL_DMA_ERROR_NONE)
  916. {
  917. /* Reset the channel internal state and reset the FIFO */
  918. hdma->Instance->CCR |= DMA_CCR_RESET;
  919. /* Update the DMA channel state */
  920. hdma->State = HAL_DMA_STATE_READY;
  921. /* Check DMA channel transfer mode */
  922. if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
  923. {
  924. /* Update the linked-list queue state */
  925. hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY;
  926. }
  927. /* Process Unlocked */
  928. __HAL_UNLOCK(hdma);
  929. /* Check transfer error callback */
  930. if (hdma->XferErrorCallback != NULL)
  931. {
  932. /* Transfer error callback */
  933. hdma->XferErrorCallback(hdma);
  934. }
  935. }
  936. }
  937. /**
  938. * @brief Register callback according to specified ID.
  939. * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET
  940. * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID.
  941. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  942. * specified DMA Channel.
  943. * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration.
  944. * @param pCallback : Pointer to private callback function.
  945. * @retval HAL status.
  946. */
  947. HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma,
  948. HAL_DMA_CallbackIDTypeDef CallbackID,
  949. void (*const pCallback)(DMA_HandleTypeDef *const _hdma))
  950. {
  951. HAL_StatusTypeDef status = HAL_OK;
  952. /* Check the DMA peripheral handle parameter */
  953. if (hdma == NULL)
  954. {
  955. return HAL_ERROR;
  956. }
  957. /* Check DMA channel state */
  958. if (hdma->State == HAL_DMA_STATE_READY)
  959. {
  960. /* Check callback ID */
  961. switch (CallbackID)
  962. {
  963. case HAL_DMA_XFER_CPLT_CB_ID:
  964. {
  965. /* Register transfer complete callback */
  966. hdma->XferCpltCallback = pCallback;
  967. break;
  968. }
  969. case HAL_DMA_XFER_HALFCPLT_CB_ID:
  970. {
  971. /* Register half transfer callback */
  972. hdma->XferHalfCpltCallback = pCallback;
  973. break;
  974. }
  975. case HAL_DMA_XFER_ERROR_CB_ID:
  976. {
  977. /* Register transfer error callback */
  978. hdma->XferErrorCallback = pCallback;
  979. break;
  980. }
  981. case HAL_DMA_XFER_ABORT_CB_ID:
  982. {
  983. /* Register abort callback */
  984. hdma->XferAbortCallback = pCallback;
  985. break;
  986. }
  987. case HAL_DMA_XFER_SUSPEND_CB_ID:
  988. {
  989. /* Register suspend callback */
  990. hdma->XferSuspendCallback = pCallback;
  991. break;
  992. }
  993. default:
  994. {
  995. /* Update error status */
  996. status = HAL_ERROR;
  997. break;
  998. }
  999. }
  1000. }
  1001. else
  1002. {
  1003. /* Update error status */
  1004. status = HAL_ERROR;
  1005. }
  1006. return status;
  1007. }
  1008. /**
  1009. * @brief Unregister callback according to specified ID.
  1010. * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET
  1011. * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID.
  1012. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  1013. * specified DMA Channel.
  1014. * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum.
  1015. * @retval HAL status.
  1016. */
  1017. HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma,
  1018. HAL_DMA_CallbackIDTypeDef CallbackID)
  1019. {
  1020. HAL_StatusTypeDef status = HAL_OK;
  1021. /* Check the DMA peripheral handle parameter */
  1022. if (hdma == NULL)
  1023. {
  1024. return HAL_ERROR;
  1025. }
  1026. /* Check DMA channel state */
  1027. if (hdma->State == HAL_DMA_STATE_READY)
  1028. {
  1029. /* Check callback ID */
  1030. switch (CallbackID)
  1031. {
  1032. case HAL_DMA_XFER_CPLT_CB_ID:
  1033. {
  1034. /* UnRegister transfer complete callback */
  1035. hdma->XferCpltCallback = NULL;
  1036. break;
  1037. }
  1038. case HAL_DMA_XFER_HALFCPLT_CB_ID:
  1039. {
  1040. /* UnRegister half transfer callback */
  1041. hdma->XferHalfCpltCallback = NULL;
  1042. break;
  1043. }
  1044. case HAL_DMA_XFER_ERROR_CB_ID:
  1045. {
  1046. /* UnRegister transfer error callback */
  1047. hdma->XferErrorCallback = NULL;
  1048. break;
  1049. }
  1050. case HAL_DMA_XFER_ABORT_CB_ID:
  1051. {
  1052. /* UnRegister abort callback */
  1053. hdma->XferAbortCallback = NULL;
  1054. break;
  1055. }
  1056. case HAL_DMA_XFER_SUSPEND_CB_ID:
  1057. {
  1058. /* UnRegister suspend callback */
  1059. hdma->XferSuspendCallback = NULL;
  1060. break;
  1061. }
  1062. case HAL_DMA_XFER_ALL_CB_ID:
  1063. {
  1064. /* UnRegister all available callbacks */
  1065. hdma->XferCpltCallback = NULL;
  1066. hdma->XferHalfCpltCallback = NULL;
  1067. hdma->XferErrorCallback = NULL;
  1068. hdma->XferAbortCallback = NULL;
  1069. hdma->XferSuspendCallback = NULL;
  1070. break;
  1071. }
  1072. default:
  1073. {
  1074. /* Update error status */
  1075. status = HAL_ERROR;
  1076. break;
  1077. }
  1078. }
  1079. }
  1080. else
  1081. {
  1082. /* Update error status */
  1083. status = HAL_ERROR;
  1084. }
  1085. return status;
  1086. }
  1087. /**
  1088. * @}
  1089. */
  1090. /** @addtogroup DMA_Exported_Functions_Group3
  1091. *
  1092. @verbatim
  1093. ======================================================================================================================
  1094. ##### State and Errors functions #####
  1095. ======================================================================================================================
  1096. [..]
  1097. This section provides functions allowing to :
  1098. (+) Check the DMA state
  1099. (+) Get error code
  1100. [..]
  1101. (+) The HAL_DMA_GetState() function allows to get the DMA channel state.
  1102. (+) The HAL_DMA_DeInit() function allows to get the DMA channel error code.
  1103. @endverbatim
  1104. * @{
  1105. */
  1106. /**
  1107. * @brief Returns the DMA channel state.
  1108. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  1109. * specified DMA Channel.
  1110. * @retval DMA state.
  1111. */
  1112. HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma)
  1113. {
  1114. /* Return the DMA channel state */
  1115. return hdma->State;
  1116. }
  1117. /**
  1118. * @brief Return the DMA channel error code.
  1119. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  1120. * specified DMA Channel.
  1121. * @retval DMA Error Code.
  1122. */
  1123. uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma)
  1124. {
  1125. /* Return the DMA channel error code */
  1126. return hdma->ErrorCode;
  1127. }
  1128. /**
  1129. * @}
  1130. */
  1131. /** @addtogroup DMA_Exported_Functions_Group4
  1132. *
  1133. @verbatim
  1134. ======================================================================================================================
  1135. ##### DMA Attributes functions #####
  1136. ======================================================================================================================
  1137. [..]
  1138. This section provides functions allowing to :
  1139. (+) Configure DMA channel secure and privilege attributes.
  1140. (+) Get DMA channel secure and privilege attributes.
  1141. (+) Lock DMA channel secure and privilege attributes configuration.
  1142. (+) Check whether DMA channel secure and privilege attributes configuration is locked or not.
  1143. [..]
  1144. (+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel security and privilege
  1145. attributes.
  1146. (+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel security and privilege attributes
  1147. configuration.
  1148. (+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel security and privilege attributes.
  1149. (+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel security and privilege
  1150. attributes lock status.
  1151. @endverbatim
  1152. * @{
  1153. */
  1154. /**
  1155. * @brief Configure the DMA channel security and privilege attribute(s).
  1156. * @note These attributes cannot be modified when the corresponding lock state is enabled.
  1157. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for
  1158. * the specified DMA Channel.
  1159. * @param ChannelAttributes : Specifies the DMA channel secure/privilege attributes.
  1160. * This parameter can be a one or a combination of @ref DMA_Channel_Attributes.
  1161. * @retval HAL Status.
  1162. */
  1163. HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes)
  1164. {
  1165. DMA_TypeDef *p_dma_instance;
  1166. uint32_t channel_idx;
  1167. /* Check the DMA peripheral handle parameter */
  1168. if (hdma == NULL)
  1169. {
  1170. return HAL_ERROR;
  1171. }
  1172. /* Check the parameters */
  1173. assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes));
  1174. /* Get DMA instance */
  1175. p_dma_instance = GET_DMA_INSTANCE(hdma);
  1176. /* Get channel index */
  1177. channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
  1178. /* Check DMA channel privilege attribute management */
  1179. if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK)
  1180. {
  1181. /* Configure DMA channel privilege attribute */
  1182. if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV)
  1183. {
  1184. p_dma_instance->PRIVCFGR |= channel_idx;
  1185. }
  1186. else
  1187. {
  1188. p_dma_instance->PRIVCFGR &= (~channel_idx);
  1189. }
  1190. }
  1191. #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
  1192. /* Check DMA channel security attribute management */
  1193. if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) == DMA_CHANNEL_ATTR_SEC_MASK)
  1194. {
  1195. /* Configure DMA channel security attribute */
  1196. if ((ChannelAttributes & DMA_CHANNEL_SEC) == DMA_CHANNEL_SEC)
  1197. {
  1198. p_dma_instance->SECCFGR |= channel_idx;
  1199. }
  1200. else
  1201. {
  1202. p_dma_instance->SECCFGR &= (~channel_idx);
  1203. }
  1204. }
  1205. /* Channel source security attribute management */
  1206. if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) == DMA_CHANNEL_ATTR_SEC_SRC_MASK)
  1207. {
  1208. /* Configure DMA channel source security attribute */
  1209. if ((ChannelAttributes & DMA_CHANNEL_SRC_SEC) == DMA_CHANNEL_SRC_SEC)
  1210. {
  1211. hdma->Instance->CTR1 |= DMA_CTR1_SSEC;
  1212. }
  1213. else
  1214. {
  1215. hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC);
  1216. }
  1217. }
  1218. /* Channel destination security attribute management */
  1219. if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) == DMA_CHANNEL_ATTR_SEC_DEST_MASK)
  1220. {
  1221. /* Configure DMA channel destination security attribute */
  1222. if ((ChannelAttributes & DMA_CHANNEL_DEST_SEC) == DMA_CHANNEL_DEST_SEC)
  1223. {
  1224. hdma->Instance->CTR1 |= DMA_CTR1_DSEC;
  1225. }
  1226. else
  1227. {
  1228. hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC);
  1229. }
  1230. }
  1231. #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
  1232. return HAL_OK;
  1233. }
  1234. /**
  1235. * @brief Get the DMA channel security and privilege attributes.
  1236. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information
  1237. * for the specified DMA Channel.
  1238. * @param pChannelAttributes : Pointer to the returned attributes.
  1239. * @retval HAL Status.
  1240. */
  1241. HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma,
  1242. uint32_t *const pChannelAttributes)
  1243. {
  1244. const DMA_TypeDef *p_dma_instance;
  1245. uint32_t attributes;
  1246. uint32_t channel_idx;
  1247. /* Check the DMA peripheral handle and channel attributes parameters */
  1248. if ((hdma == NULL) || (pChannelAttributes == NULL))
  1249. {
  1250. return HAL_ERROR;
  1251. }
  1252. /* Get DMA instance */
  1253. p_dma_instance = GET_DMA_INSTANCE(hdma);
  1254. /* Get channel index */
  1255. channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
  1256. /* Get DMA channel privilege attribute */
  1257. attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV;
  1258. #if defined (DMA_SECCFGR_SEC0)
  1259. /* Get DMA channel security attribute */
  1260. attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC;
  1261. /* Get DMA channel source security attribute */
  1262. attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC;
  1263. /* Get DMA channel destination security attribute */
  1264. attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC;
  1265. #endif /* DMA_SECCFGR_SEC0 */
  1266. /* return value */
  1267. *pChannelAttributes = attributes;
  1268. return HAL_OK;
  1269. }
  1270. #if defined (DMA_RCFGLOCKR_LOCK0)
  1271. #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
  1272. /**
  1273. * @brief Lock the DMA channel security and privilege attribute(s).
  1274. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  1275. * specified DMA Channel.
  1276. * @retval HAL Status.
  1277. */
  1278. HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma)
  1279. {
  1280. DMA_TypeDef *p_dma_instance;
  1281. uint32_t channel_idx;
  1282. /* Check the DMA peripheral handle parameter */
  1283. if (hdma == NULL)
  1284. {
  1285. return HAL_ERROR;
  1286. }
  1287. /* Get DMA instance */
  1288. p_dma_instance = GET_DMA_INSTANCE(hdma);
  1289. /* Get channel index */
  1290. channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
  1291. /* Lock the DMA channel privilege and security attributes */
  1292. p_dma_instance->RCFGLOCKR |= channel_idx;
  1293. return HAL_OK;
  1294. }
  1295. #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
  1296. /**
  1297. * @brief Get the security and privilege attribute lock state of a DMA channel.
  1298. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  1299. * specified DMA Channel.
  1300. * @param pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or
  1301. * DMA_CHANNEL_ATTRIBUTE_LOCKED).
  1302. * @retval HAL status.
  1303. */
  1304. HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState)
  1305. {
  1306. const DMA_TypeDef *p_dma_instance;
  1307. uint32_t channel_idx;
  1308. /* Check the DMA peripheral handle and lock state parameters */
  1309. if ((hdma == NULL) || (pLockState == NULL))
  1310. {
  1311. return HAL_ERROR;
  1312. }
  1313. /* Get DMA instance */
  1314. p_dma_instance = GET_DMA_INSTANCE(hdma);
  1315. /* Get channel index */
  1316. channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU);
  1317. /* Get channel lock attribute state */
  1318. *pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \
  1319. DMA_CHANNEL_ATTRIBUTE_LOCKED;
  1320. return HAL_OK;
  1321. }
  1322. #endif /* DMA_RCFGLOCKR_LOCK0 */
  1323. /**
  1324. * @}
  1325. */
  1326. /**
  1327. * @}
  1328. */
  1329. /* Private functions -------------------------------------------------------------------------------------------------*/
  1330. /** @defgroup DMA_Private_Functions DMA Private Functions
  1331. * @brief DMA Private Functions
  1332. * @{
  1333. */
  1334. /**
  1335. * @brief Set the DMA channel normal transfer parameters.
  1336. * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  1337. * specified DMA Channel.
  1338. * @param SrcAddress : The source data address.
  1339. * @param DstAddress : The destination data address.
  1340. * @param SrcDataSize : The length of data to be transferred from source to destination in bytes.
  1341. * @retval None.
  1342. */
  1343. static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma,
  1344. uint32_t SrcAddress,
  1345. uint32_t DstAddress,
  1346. uint32_t SrcDataSize)
  1347. {
  1348. /* Configure the DMA channel data size */
  1349. MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT));
  1350. /* Clear all interrupt flags */
  1351. __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP |
  1352. DMA_FLAG_TO);
  1353. /* Configure DMA channel source address */
  1354. hdma->Instance->CSAR = SrcAddress;
  1355. /* Configure DMA channel destination address */
  1356. hdma->Instance->CDAR = DstAddress;
  1357. }
  1358. /**
  1359. * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef.
  1360. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the
  1361. * specified DMA Channel.
  1362. * @retval None.
  1363. */
  1364. static void DMA_Init(DMA_HandleTypeDef const *const hdma)
  1365. {
  1366. uint32_t tmpreg;
  1367. /* Prepare DMA Channel Control Register (CCR) value *****************************************************************/
  1368. tmpreg = hdma->Init.Priority;
  1369. /* Write DMA Channel Control Register (CCR) */
  1370. MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg);
  1371. /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/
  1372. tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth;
  1373. /* Add parameters specific to GPDMA */
  1374. if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
  1375. {
  1376. tmpreg |= (hdma->Init.TransferAllocatedPort |
  1377. (((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) |
  1378. (((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1));
  1379. }
  1380. /* Write DMA Channel Transfer Register 1 (CTR1) */
  1381. #if defined (DMA_CTR1_SSEC)
  1382. MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg);
  1383. #else
  1384. WRITE_REG(hdma->Instance->CTR1, tmpreg);
  1385. #endif /* DMA_CTR1_SSEC */
  1386. /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/
  1387. tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode;
  1388. /* Memory to Peripheral Transfer */
  1389. if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
  1390. {
  1391. if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U)
  1392. {
  1393. tmpreg |= DMA_CTR2_DREQ;
  1394. }
  1395. }
  1396. /* Memory to Memory Transfer */
  1397. else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY)
  1398. {
  1399. tmpreg |= DMA_CTR2_SWREQ;
  1400. }
  1401. else
  1402. {
  1403. /* Nothing to do */
  1404. }
  1405. /* Set DMA channel operation mode */
  1406. tmpreg |= hdma->Init.Mode;
  1407. /* Write DMA Channel Transfer Register 2 (CTR2) */
  1408. MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM |
  1409. DMA_CTR2_PFREQ | DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ |
  1410. DMA_CTR2_REQSEL), tmpreg);
  1411. /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/
  1412. WRITE_REG(hdma->Instance->CBR1, 0U);
  1413. /* If 2D Addressing is supported by current channel */
  1414. if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U)
  1415. {
  1416. /* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/
  1417. WRITE_REG(hdma->Instance->CTR3, 0U);
  1418. /* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/
  1419. WRITE_REG(hdma->Instance->CBR2, 0U);
  1420. }
  1421. /* Write DMA Channel linked-list address register (CLLR) ************************************************************/
  1422. WRITE_REG(hdma->Instance->CLLR, 0U);
  1423. }
  1424. /**
  1425. * @}
  1426. */
  1427. #endif /* HAL_DMA_MODULE_ENABLED */
  1428. /**
  1429. * @}
  1430. */
  1431. /**
  1432. * @}
  1433. */